refactor(arm): refactor secure TL initialization

The initialization logic for the secure transfer list is currently
scattered and duplicated across platform setup code. This not only leads
to ineffi

refactor(arm): refactor secure TL initialization

The initialization logic for the secure transfer list is currently
scattered and duplicated across platform setup code. This not only leads
to inefficiency but also complicates access to transfer lists from other
parts of the code without invoking setup functions. For instance,
arm_bl2_setup_next_ep_info acts as a thin wrapper in arm_bl2_setup.c to
provide access to the secure transfer list.

To streamline the interface, all setup code has been consolidated into a
central location.

Change-Id: I99d2a567ff39df88baa57e7e08607fccb8af189c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(arm): resolve dangling comments around macros

Fix dangling comments around define guards, addressing leftovers from
fe94a21a6 ("fix(arm): move HW_CONFIG relocation into BL31") which
implicitly r

fix(arm): resolve dangling comments around macros

Fix dangling comments around define guards, addressing leftovers from
fe94a21a6 ("fix(arm): move HW_CONFIG relocation into BL31") which
implicitly removed constraints on using HW_CONFIG with RESET_TO_BL2.

Change-Id: I19d61812fed6fa4b668875e5bf4eafd1a8a660f6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(tc): define status to fix SPM tests

The failure was caused by missing a variable definition, `status`
in the RSE initialisation patch.

Change-Id: I937a39e20fae39f3a6d14fe66af578c166545301
Signe

fix(tc): define status to fix SPM tests

The failure was caused by missing a variable definition, `status`
in the RSE initialisation patch.

Change-Id: I937a39e20fae39f3a6d14fe66af578c166545301
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(css): turn the redistributor off on PSCI CPU_OFF

When GICR_WAKER.ProcessorSleep == 1 (i.e. after gicv3_cpuif_disable())
the GIC will assert the WakeRequest signal to try and wake the core up
ins

fix(css): turn the redistributor off on PSCI CPU_OFF

When GICR_WAKER.ProcessorSleep == 1 (i.e. after gicv3_cpuif_disable())
the GIC will assert the WakeRequest signal to try and wake the core up
instead of delivering an interrupt. This is useful when a core is in
some kind of suspend state.

However, when the core is properly off (CPU_OFF), it shouldn't get woken
up in any way other than a CPU_ON call. In the general case interrupts
would be routed away so this doesn't matter. But in case they aren't, we
want the core to stay off.

So turn the redistributor off on CPU_OFF calls. This will prevent the
WakeRequest from being sent.

Change-Id: I7f20591d1c83a4a9639281ef86caa79d6669b536
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(psa): increase psa-mbedtls heap size for rsa" into integration

Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qe

Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qemu-sbsa): configure GPT based on system RAM
feat(qemu-sbsa): adjust DT memory start address when supporting RME
feat(qemu-sbsa): relocate DT after the RMM when RME is enabled
feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE
feat(qemu-sbsa): increase maximum FIP size
refactor(qemu-sbsa): move all DT related functions to sbsa_platform.c
refactor(qemu-sbsa): create accessor functions for platform info
refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful
refactor(qemu-sbsa): move DT related structures to their own header
refactor(qemu-sbsa): rename struct dynamic_platform_info
refactor(qemu): make L0GPT size configurable
refactor(qemu): move GPT setup to BL31
fix(qemu-sbsa): fix compilation error when accessing DT functions

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Merge "feat(mt8196): enable DP and eDP for mt8196" into integration

Merge "feat(stm32mp2): add FWU support" into integration

Merge changes I7854e1ae,I214e4b2b,I000573e5 into integration

* changes:
feat(stm32mp2): add a runtime service for STGEN configuration
feat(stm32mp2): add common SMC runtime services
feat(stm32

Merge changes I7854e1ae,I214e4b2b,I000573e5 into integration

* changes:
feat(stm32mp2): add a runtime service for STGEN configuration
feat(stm32mp2): add common SMC runtime services
feat(stm32mp1): rework SVC services

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fix(tc): eliminate unneeded MbedTLS dependency

The rse_platform_api.h file includes certain MbedTLS headers,
introducing an unnecessary dependency when building the TC
platform with RSE support unco

fix(tc): eliminate unneeded MbedTLS dependency

The rse_platform_api.h file includes certain MbedTLS headers,
introducing an unnecessary dependency when building the TC
platform with RSE support unconditionally.
However, these headers are not required, as the BL31
implementation only initializes RSE communication,
which does not rely on MbedTLS.

Change-Id: If45122aaf158be128f8978422fd870dbb0a0d090
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(mediatek): add vcp driver support

It is excepted that kernel vcp can request the vcp hw do
some security setting via SMC call services.

Signed-off-by: Xiangzhi Tang <xiangzhi.tang@mediatek.cor

feat(mediatek): add vcp driver support

It is excepted that kernel vcp can request the vcp hw do
some security setting via SMC call services.

Signed-off-by: Xiangzhi Tang <xiangzhi.tang@mediatek.corp-partner.google.com>
Change-Id: Ib5c01c1d72b3483262dcd821878e6e53ba9c681c

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fix(rk3399): fix unquoted .incbin for clang

While GCC doesn't complain about anything for .incbin, clang does:
"""
<instantiation>:6:10: error: expected string in '.incbin' directive
.incbin /build

fix(rk3399): fix unquoted .incbin for clang

While GCC doesn't complain about anything for .incbin, clang does:
"""
<instantiation>:6:10: error: expected string in '.incbin' directive
.incbin /build/rk3399/release/m0/rk3399m0.bin
^
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:20:1: note: while in macro instantiation
INCBIN """/build/rk3399/release/m0/rk3399m0.bin""", "rk3399m0_bin", ".sram.incbin"
^
<instantiation>:6:10: error: expected string in '.incbin' directive
.incbin /build/rk3399/release/m0/rk3399m0pmu.bin
^
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:21:1: note: while in macro instantiation
INCBIN """/build/rk3399/release/m0/rk3399m0pmu.bin""", "rk3399m0pmu_bin", ".pmusram.incbin"
^
"""

Adding quotes around \file in .incbin fixes the clang issue but GCC now
complains:
"""
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S: Assembler messages:
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: junk at end of line, first unrecognized character is `/'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:20: Info: macro invoked from here
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: unable to include `./'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:20: Info: macro invoked from here
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: junk at end of line, first unrecognized character is `/'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:21: Info: macro invoked from here
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: unable to include `./'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:21: Info: macro invoked from here
"""

Considering that the symbol is defined with escaped quotes, it is
probably safe to remove the double quotes around the INBCIN macro
parameter, so let's do that to make both compilers happy.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Change-Id: Id18b0341353ffc00e44e2d3c643ccdd05cc20c4f

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fix(rk3399): mark INCBIN-generated sections as SHF_ALLOC

When assembling with Clang, sections generated via the `INCBIN` macro
are not assigned the `SHF_ALLOC` attribute, and the linker therefore
do

fix(rk3399): mark INCBIN-generated sections as SHF_ALLOC

When assembling with Clang, sections generated via the `INCBIN` macro
are not assigned the `SHF_ALLOC` attribute, and the linker therefore
does not know to include them in the binary.

This change is simple: explicitly tell the assembler that the section
should have the `SHF_ALLOC` attribute.

For reference: https://man7.org/linux/man-pages/man5/elf.5.html

> SHF_ALLOC
> This section occupies memory during process execution. Some
> control sections do not reside in the memory image of an object
> file. This attribute is off for those sections.

Change-Id: I626162eae9030b5ffbd03af2be76f89a248af9ca
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

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Merge changes from topic "clang-rockchip" into integration

* changes:
build(rk3399): m0: Makefile: respect verbosity for linkerfile
build(rk3399): m0: fail linker and assembler on warnings
bui

Merge changes from topic "clang-rockchip" into integration

* changes:
build(rk3399): m0: Makefile: respect verbosity for linkerfile
build(rk3399): m0: fail linker and assembler on warnings
build(rk3399): m0: remove redundant M0_CROSS_COMPILE
feat(build): rk3399: m0: add support for new binutils versions
fix(rk3399): m0: Makefile: fix outside array bounds warning
refactor(rk3399): m0: Makefile: use same tools as in build_macros.mk
refactor(rk3399): m0: Makefile: specify ARCH to be rk3399-m0
fix(rk3588): pmu: fix assembly symbol redefinition
fix(rockchip): pmu: Do not mark already defined functions as weak
fix(rk3399): dram: Fix build with gcc 11
fix(rk3288): remove unused function
fix(px30): remove unused function

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Merge "fix(romlib): romlib build without MbedTLS" into integration

Merge "feat(tc): initialize MHU channels with RSE" into integration

Merge "fix(tc): map mem_protect flash region" into integration

feat(stm32mp2): add a runtime service for STGEN configuration

Other component such as OP-TEE may have the responsibility for
STGEN configuration but updating Arm CNTFRQ can only be done from
EL3. Th

feat(stm32mp2): add a runtime service for STGEN configuration

Other component such as OP-TEE may have the responsibility for
STGEN configuration but updating Arm CNTFRQ can only be done from
EL3. Therefore, implement a SiP SMC handler for this purpose and
a runtime service to catch SIP SMCs.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I7854e1ae6328f149798b43d52bb1ecdf71a5aa69

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feat(stm32mp2): add common SMC runtime services

Implement the common SMC runtime services for stm32mp2 platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Max

feat(stm32mp2): add common SMC runtime services

Implement the common SMC runtime services for stm32mp2 platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I214e4b2bfba439572c079bbc9ffb62bc87793ce9

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feat(stm32mp1): rework SVC services

Having two generations of STM32MPX using the same SMCCC protocol,
rework the SVC services setup to put in common what can be put
in common and implement platform-

feat(stm32mp1): rework SVC services

Having two generations of STM32MPX using the same SMCCC protocol,
rework the SVC services setup to put in common what can be put
in common and implement platform-specific handlers.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I000573e50d55dc70163c2657c12cc84085416f6b

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Merge changes Ib1b810df,I5492bab5 into integration

* changes:
feat(tc): add dsu pmu node for TC4
feat(tc): enable DSU PMU el1 access for TC4

Merge "feat(qti): platform support for qcs615" into integration

feat(qti): platform support for qcs615

Change-Id: Ibbe78a196d77530fa9d94d7d12b2f08a4b66d62e
Signed-off-by: Amarinder Singh Sethi <quic_assethi@quicinc.com>

feat(fpmr): disable FPMR trap

This patch enables support of FEAT_FPMR by enabling access
to FPMR register. It achieves it by setting the EnFPM bit of
SCR_EL3. This feature is currently enabled for N

feat(fpmr): disable FPMR trap

This patch enables support of FEAT_FPMR by enabling access
to FPMR register. It achieves it by setting the EnFPM bit of
SCR_EL3. This feature is currently enabled for NS world only.

Reference:
https://developer.arm.com/documentation/109697/2024_09/
Feature-descriptions/The-Armv9-5-architecture-extension?lang=en

Change-Id: I580c409b9b22f8ead0737502280fb9093a3d5dd2
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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fix(psa): increase psa-mbedtls heap size for rsa

The value assigned for the mbedtls heap size for large
rsa keys was too small when PSA_CRYPTO is set to 1,
leading to run-time failures if one was to

fix(psa): increase psa-mbedtls heap size for rsa

The value assigned for the mbedtls heap size for large
rsa keys was too small when PSA_CRYPTO is set to 1,
leading to run-time failures if one was to attempt
to use a large RSA key with PSA_CRYPTO=1.

Change-Id: Id9b2648ae911879f483f1b88301f28694af0721d
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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