1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <bl1/bl1.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <lib/fconf/fconf.h> 16 #include <lib/fconf/fconf_dyn_cfg_getter.h> 17 #if TRANSFER_LIST 18 #include <lib/transfer_list.h> 19 #endif 20 #include <lib/utils.h> 21 #include <lib/xlat_tables/xlat_tables_compat.h> 22 #include <plat/arm/common/plat_arm.h> 23 #include <plat/common/platform.h> 24 25 /* Weak definitions may be overridden in specific ARM standard platform */ 26 #pragma weak bl1_early_platform_setup 27 #pragma weak bl1_plat_arch_setup 28 #pragma weak bl1_plat_sec_mem_layout 29 #pragma weak arm_bl1_early_platform_setup 30 #pragma weak bl1_plat_prepare_exit 31 #pragma weak bl1_plat_get_next_image_id 32 #pragma weak plat_arm_bl1_fwu_needed 33 #pragma weak arm_bl1_plat_arch_setup 34 #pragma weak arm_bl1_platform_setup 35 36 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 37 bl1_tzram_layout.total_base, \ 38 bl1_tzram_layout.total_size, \ 39 MT_MEMORY | MT_RW | EL3_PAS) 40 /* 41 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 42 * otherwise one region is defined containing both 43 */ 44 #if SEPARATE_CODE_AND_RODATA 45 #define MAP_BL1_RO MAP_REGION_FLAT( \ 46 BL_CODE_BASE, \ 47 BL1_CODE_END - BL_CODE_BASE, \ 48 MT_CODE | EL3_PAS), \ 49 MAP_REGION_FLAT( \ 50 BL1_RO_DATA_BASE, \ 51 BL1_RO_DATA_END \ 52 - BL_RO_DATA_BASE, \ 53 MT_RO_DATA | EL3_PAS) 54 #else 55 #define MAP_BL1_RO MAP_REGION_FLAT( \ 56 BL_CODE_BASE, \ 57 BL1_CODE_END - BL_CODE_BASE, \ 58 MT_CODE | EL3_PAS) 59 #endif 60 61 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 62 static meminfo_t bl1_tzram_layout; 63 64 /* Boolean variable to hold condition whether firmware update needed or not */ 65 static bool is_fwu_needed; 66 67 struct transfer_list_header *secure_tl; 68 69 struct meminfo *bl1_plat_sec_mem_layout(void) 70 { 71 return &bl1_tzram_layout; 72 } 73 74 /******************************************************************************* 75 * BL1 specific platform actions shared between ARM standard platforms. 76 ******************************************************************************/ 77 void arm_bl1_early_platform_setup(void) 78 { 79 80 #if !ARM_DISABLE_TRUSTED_WDOG 81 /* Enable watchdog */ 82 plat_arm_secure_wdt_start(); 83 #endif 84 85 /* Initialize the console to provide early debug support */ 86 arm_console_boot_init(); 87 88 /* Allow BL1 to see the whole Trusted RAM */ 89 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 90 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 91 92 #if TRANSFER_LIST 93 secure_tl = transfer_list_ensure((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE, 94 PLAT_ARM_FW_HANDOFF_SIZE); 95 assert(secure_tl != NULL); 96 #endif 97 } 98 99 void bl1_early_platform_setup(void) 100 { 101 arm_bl1_early_platform_setup(); 102 103 /* 104 * Initialize Interconnect for this cluster during cold boot. 105 * No need for locks as no other CPU is active. 106 */ 107 plat_arm_interconnect_init(); 108 /* 109 * Enable Interconnect coherency for the primary CPU's cluster. 110 */ 111 plat_arm_interconnect_enter_coherency(); 112 } 113 114 /****************************************************************************** 115 * Perform the very early platform specific architecture setup shared between 116 * ARM standard platforms. This only does basic initialization. Later 117 * architectural setup (bl1_arch_setup()) does not do anything platform 118 * specific. 119 *****************************************************************************/ 120 void arm_bl1_plat_arch_setup(void) 121 { 122 #if USE_COHERENT_MEM 123 /* Ensure ARM platforms don't use coherent memory in BL1. */ 124 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 125 #endif 126 127 const mmap_region_t bl_regions[] = { 128 MAP_BL1_TOTAL, 129 MAP_BL1_RO, 130 #if USE_ROMLIB 131 ARM_MAP_ROMLIB_CODE, 132 ARM_MAP_ROMLIB_DATA, 133 #endif 134 {0} 135 }; 136 137 setup_page_tables(bl_regions, plat_arm_get_mmap()); 138 #ifdef __aarch64__ 139 enable_mmu_el3(0); 140 #else 141 enable_mmu_svc_mon(0); 142 #endif /* __aarch64__ */ 143 144 arm_setup_romlib(); 145 } 146 147 void bl1_plat_arch_setup(void) 148 { 149 arm_bl1_plat_arch_setup(); 150 } 151 152 /* 153 * Perform the platform specific architecture setup shared between 154 * ARM standard platforms. 155 */ 156 void arm_bl1_platform_setup(void) 157 { 158 const struct dyn_cfg_dtb_info_t *config_info __unused; 159 uint32_t fw_config_max_size __unused; 160 image_info_t config_image_info __unused; 161 struct transfer_list_entry *te __unused; 162 163 image_desc_t *desc; 164 165 int err = -1; 166 167 /* Initialise the IO layer and register platform IO devices */ 168 plat_arm_io_setup(); 169 170 /* Check if we need FWU before further processing */ 171 is_fwu_needed = plat_arm_bl1_fwu_needed(); 172 if (is_fwu_needed) { 173 ERROR("Skip platform setup as FWU detected\n"); 174 return; 175 } 176 177 #if TRANSFER_LIST 178 te = transfer_list_add(secure_tl, TL_TAG_TB_FW_CONFIG, 179 ARM_TB_FW_CONFIG_MAX_SIZE, NULL); 180 assert(te != NULL); 181 182 /* 183 * Set the load address of TB_FW_CONFIG in the data section of the TE just 184 * allocated in the secure transfer list. 185 */ 186 SET_PARAM_HEAD(&config_image_info, PARAM_IMAGE_BINARY, VERSION_2, 0); 187 config_image_info.image_base = (uintptr_t)transfer_list_entry_data(te); 188 config_image_info.image_max_size = te->data_size; 189 190 VERBOSE("FCONF: Loading config with image ID: %u\n", TB_FW_CONFIG_ID); 191 err = load_auth_image(TB_FW_CONFIG_ID, &config_image_info); 192 if (err != 0) { 193 VERBOSE("Failed to load config %u\n", TB_FW_CONFIG_ID); 194 plat_error_handler(err); 195 } 196 197 transfer_list_update_checksum(secure_tl); 198 fconf_populate("TB_FW", (uintptr_t)transfer_list_entry_data(te)); 199 #else 200 /* Set global DTB info for fixed fw_config information */ 201 fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE; 202 set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, FW_CONFIG_ID); 203 204 /* Fill the device tree information struct with the info from the config dtb */ 205 err = fconf_load_config(FW_CONFIG_ID); 206 if (err < 0) { 207 ERROR("Loading of FW_CONFIG failed %d\n", err); 208 plat_error_handler(err); 209 } 210 211 /* 212 * FW_CONFIG loaded successfully. If FW_CONFIG device tree parsing 213 * is successful then load TB_FW_CONFIG device tree. 214 */ 215 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID); 216 if (config_info != NULL) { 217 err = fconf_populate_dtb_registry(config_info->config_addr); 218 if (err < 0) { 219 ERROR("Parsing of FW_CONFIG failed %d\n", err); 220 plat_error_handler(err); 221 } 222 223 /* load TB_FW_CONFIG */ 224 err = fconf_load_config(TB_FW_CONFIG_ID); 225 if (err < 0) { 226 ERROR("Loading of TB_FW_CONFIG failed %d\n", err); 227 plat_error_handler(err); 228 } 229 } else { 230 ERROR("Invalid FW_CONFIG address\n"); 231 plat_error_handler(err); 232 } 233 #endif /* TRANSFER_LIST */ 234 235 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 236 237 #if TRANSFER_LIST 238 transfer_list_set_handoff_args(secure_tl, &desc->ep_info); 239 #else 240 /* The BL2 ep_info arg0 is modified to point to FW_CONFIG */ 241 assert(desc != NULL); 242 desc->ep_info.args.arg0 = config_info->config_addr; 243 #endif /* TRANSFER_LIST */ 244 245 #if CRYPTO_SUPPORT 246 /* Share the Mbed TLS heap info with other images */ 247 arm_bl1_set_mbedtls_heap(); 248 #endif /* CRYPTO_SUPPORT */ 249 250 /* 251 * Allow access to the System counter timer module and program 252 * counter frequency for non secure images during FWU 253 */ 254 #ifdef ARM_SYS_TIMCTL_BASE 255 arm_configure_sys_timer(); 256 #endif 257 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER) 258 write_cntfrq_el0(plat_get_syscnt_freq2()); 259 #endif 260 } 261 262 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 263 { 264 #if !ARM_DISABLE_TRUSTED_WDOG 265 /* Disable watchdog before leaving BL1 */ 266 plat_arm_secure_wdt_stop(); 267 #endif 268 269 #ifdef EL3_PAYLOAD_BASE 270 /* 271 * Program the EL3 payload's entry point address into the CPUs mailbox 272 * in order to release secondary CPUs from their holding pen and make 273 * them jump there. 274 */ 275 plat_arm_program_trusted_mailbox(ep_info->pc); 276 dsbsy(); 277 sev(); 278 #endif 279 } 280 281 /* 282 * On Arm platforms, the FWU process is triggered when the FIP image has 283 * been tampered with. 284 */ 285 bool plat_arm_bl1_fwu_needed(void) 286 { 287 return !arm_io_is_toc_valid(); 288 } 289 290 /******************************************************************************* 291 * The following function checks if Firmware update is needed, 292 * by checking if TOC in FIP image is valid or not. 293 ******************************************************************************/ 294 unsigned int bl1_plat_get_next_image_id(void) 295 { 296 return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID; 297 } 298 299 // Use the default implementation of this function when Firmware Handoff is 300 // disabled to avoid duplicating its logic. 301 #if TRANSFER_LIST 302 int bl1_plat_handle_post_image_load(unsigned int image_id) 303 { 304 image_desc_t *image_desc __unused; 305 306 assert(image_id == BL2_IMAGE_ID); 307 struct transfer_list_entry *te; 308 309 /* Convey this information to BL2 via its TL. */ 310 te = transfer_list_add(secure_tl, TL_TAG_SRAM_LAYOUT64, 311 sizeof(meminfo_t), NULL); 312 assert(te != NULL); 313 314 bl1_plat_calc_bl2_layout(&bl1_tzram_layout, 315 (meminfo_t *)transfer_list_entry_data(te)); 316 317 transfer_list_update_checksum(secure_tl); 318 319 /** 320 * Before exiting make sure the contents of the TL are flushed in case there's no 321 * support for hardware cache coherency. 322 */ 323 flush_dcache_range((uintptr_t)secure_tl, secure_tl->size); 324 return 0; 325 } 326 #endif /* TRANSFER_LIST*/ 327