1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pmuv3.h> 34 #include <lib/extensions/sme.h> 35 #include <lib/extensions/spe.h> 36 #include <lib/extensions/sve.h> 37 #include <lib/extensions/sysreg128.h> 38 #include <lib/extensions/sys_reg_trace.h> 39 #include <lib/extensions/tcr2.h> 40 #include <lib/extensions/trbe.h> 41 #include <lib/extensions/trf.h> 42 #include <lib/utils.h> 43 44 #if ENABLE_FEAT_TWED 45 /* Make sure delay value fits within the range(0-15) */ 46 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 47 #endif /* ENABLE_FEAT_TWED */ 48 49 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 50 static bool has_secure_perworld_init; 51 52 static void manage_extensions_common(cpu_context_t *ctx); 53 static void manage_extensions_nonsecure(cpu_context_t *ctx); 54 static void manage_extensions_secure(cpu_context_t *ctx); 55 static void manage_extensions_secure_per_world(void); 56 57 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 58 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 59 { 60 u_register_t sctlr_elx, actlr_elx; 61 62 /* 63 * Initialise SCTLR_EL1 to the reset value corresponding to the target 64 * execution state setting all fields rather than relying on the hw. 65 * Some fields have architecturally UNKNOWN reset values and these are 66 * set to zero. 67 * 68 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 69 * 70 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 71 * required by PSCI specification) 72 */ 73 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 74 if (GET_RW(ep->spsr) == MODE_RW_64) { 75 sctlr_elx |= SCTLR_EL1_RES1; 76 } else { 77 /* 78 * If the target execution state is AArch32 then the following 79 * fields need to be set. 80 * 81 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 82 * instructions are not trapped to EL1. 83 * 84 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 85 * instructions are not trapped to EL1. 86 * 87 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 88 * CP15DMB, CP15DSB, and CP15ISB instructions. 89 */ 90 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 91 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 92 } 93 94 /* 95 * If workaround of errata 764081 for Cortex-A75 is used then set 96 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 97 */ 98 if (errata_a75_764081_applies()) { 99 sctlr_elx |= SCTLR_IESB_BIT; 100 } 101 102 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 103 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 104 105 /* 106 * Base the context ACTLR_EL1 on the current value, as it is 107 * implementation defined. The context restore process will write 108 * the value from the context to the actual register and can cause 109 * problems for processor cores that don't expect certain bits to 110 * be zero. 111 */ 112 actlr_elx = read_actlr_el1(); 113 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 114 } 115 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 116 117 /****************************************************************************** 118 * This function performs initializations that are specific to SECURE state 119 * and updates the cpu context specified by 'ctx'. 120 *****************************************************************************/ 121 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 122 { 123 u_register_t scr_el3; 124 el3_state_t *state; 125 126 state = get_el3state_ctx(ctx); 127 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 128 129 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 130 /* 131 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 132 * indicated by the interrupt routing model for BL31. 133 */ 134 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 135 #endif 136 137 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 138 if (is_feat_mte2_supported()) { 139 scr_el3 |= SCR_ATA_BIT; 140 } 141 142 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 143 144 /* 145 * Initialize EL1 context registers unless SPMC is running 146 * at S-EL2. 147 */ 148 #if (!SPMD_SPM_AT_SEL2) 149 setup_el1_context(ctx, ep); 150 #endif 151 152 manage_extensions_secure(ctx); 153 154 /** 155 * manage_extensions_secure_per_world api has to be executed once, 156 * as the registers getting initialised, maintain constant value across 157 * all the cpus for the secure world. 158 * Henceforth, this check ensures that the registers are initialised once 159 * and avoids re-initialization from multiple cores. 160 */ 161 if (!has_secure_perworld_init) { 162 manage_extensions_secure_per_world(); 163 } 164 } 165 166 #if ENABLE_RME 167 /****************************************************************************** 168 * This function performs initializations that are specific to REALM state 169 * and updates the cpu context specified by 'ctx'. 170 *****************************************************************************/ 171 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 172 { 173 u_register_t scr_el3; 174 el3_state_t *state; 175 176 state = get_el3state_ctx(ctx); 177 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 178 179 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 180 181 /* CSV2 version 2 and above */ 182 if (is_feat_csv2_2_supported()) { 183 /* Enable access to the SCXTNUM_ELx registers. */ 184 scr_el3 |= SCR_EnSCXT_BIT; 185 } 186 187 if (is_feat_sctlr2_supported()) { 188 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 189 * SCTLR2_ELx registers. 190 */ 191 scr_el3 |= SCR_SCTLR2En_BIT; 192 } 193 194 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 195 } 196 #endif /* ENABLE_RME */ 197 198 /****************************************************************************** 199 * This function performs initializations that are specific to NON-SECURE state 200 * and updates the cpu context specified by 'ctx'. 201 *****************************************************************************/ 202 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 203 { 204 u_register_t scr_el3; 205 el3_state_t *state; 206 207 state = get_el3state_ctx(ctx); 208 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 209 210 /* SCR_NS: Set the NS bit */ 211 scr_el3 |= SCR_NS_BIT; 212 213 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 214 if (is_feat_mte2_supported()) { 215 scr_el3 |= SCR_ATA_BIT; 216 } 217 218 #if !CTX_INCLUDE_PAUTH_REGS 219 /* 220 * Pointer Authentication feature, if present, is always enabled by default 221 * for Non secure lower exception levels. We do not have an explicit 222 * flag to set it. 223 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 224 * exception levels of secure and realm worlds. 225 * 226 * To prevent the leakage between the worlds during world switch, 227 * we enable it only for the non-secure world. 228 * 229 * If the Secure/realm world wants to use pointer authentication, 230 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 231 * it will be enabled globally for all the contexts. 232 * 233 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 234 * other than EL3 235 * 236 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 237 * than EL3 238 */ 239 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 240 241 #endif /* CTX_INCLUDE_PAUTH_REGS */ 242 243 #if HANDLE_EA_EL3_FIRST_NS 244 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 245 scr_el3 |= SCR_EA_BIT; 246 #endif 247 248 #if RAS_TRAP_NS_ERR_REC_ACCESS 249 /* 250 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 251 * and RAS ERX registers from EL1 and EL2(from any security state) 252 * are trapped to EL3. 253 * Set here to trap only for NS EL1/EL2 254 * 255 */ 256 scr_el3 |= SCR_TERR_BIT; 257 #endif 258 259 /* CSV2 version 2 and above */ 260 if (is_feat_csv2_2_supported()) { 261 /* Enable access to the SCXTNUM_ELx registers. */ 262 scr_el3 |= SCR_EnSCXT_BIT; 263 } 264 265 #ifdef IMAGE_BL31 266 /* 267 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 268 * indicated by the interrupt routing model for BL31. 269 */ 270 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 271 #endif 272 273 if (is_feat_the_supported()) { 274 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 275 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 276 */ 277 scr_el3 |= SCR_RCWMASKEn_BIT; 278 } 279 280 if (is_feat_sctlr2_supported()) { 281 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 282 * SCTLR2_ELx registers. 283 */ 284 scr_el3 |= SCR_SCTLR2En_BIT; 285 } 286 287 if (is_feat_d128_supported()) { 288 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 289 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 290 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 291 */ 292 scr_el3 |= SCR_D128En_BIT; 293 } 294 295 if (is_feat_fpmr_supported()) { 296 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 297 * register. 298 */ 299 scr_el3 |= SCR_EnFPM_BIT; 300 } 301 302 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 303 304 /* Initialize EL2 context registers */ 305 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 306 307 /* 308 * Initialize SCTLR_EL2 context register with reset value. 309 */ 310 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 311 312 if (is_feat_hcx_supported()) { 313 /* 314 * Initialize register HCRX_EL2 with its init value. 315 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 316 * chance that this can lead to unexpected behavior in lower 317 * ELs that have not been updated since the introduction of 318 * this feature if not properly initialized, especially when 319 * it comes to those bits that enable/disable traps. 320 */ 321 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 322 HCRX_EL2_INIT_VAL); 323 } 324 325 if (is_feat_fgt_supported()) { 326 /* 327 * Initialize HFG*_EL2 registers with a default value so legacy 328 * systems unaware of FEAT_FGT do not get trapped due to their lack 329 * of initialization for this feature. 330 */ 331 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 332 HFGITR_EL2_INIT_VAL); 333 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 334 HFGRTR_EL2_INIT_VAL); 335 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 336 HFGWTR_EL2_INIT_VAL); 337 } 338 #else 339 /* Initialize EL1 context registers */ 340 setup_el1_context(ctx, ep); 341 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 342 343 manage_extensions_nonsecure(ctx); 344 } 345 346 /******************************************************************************* 347 * The following function performs initialization of the cpu_context 'ctx' 348 * for first use that is common to all security states, and sets the 349 * initial entrypoint state as specified by the entry_point_info structure. 350 * 351 * The EE and ST attributes are used to configure the endianness and secure 352 * timer availability for the new execution context. 353 ******************************************************************************/ 354 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 355 { 356 u_register_t scr_el3; 357 u_register_t mdcr_el3; 358 el3_state_t *state; 359 gp_regs_t *gp_regs; 360 361 state = get_el3state_ctx(ctx); 362 363 /* Clear any residual register values from the context */ 364 zeromem(ctx, sizeof(*ctx)); 365 366 /* 367 * The lower-EL context is zeroed so that no stale values leak to a world. 368 * It is assumed that an all-zero lower-EL context is good enough for it 369 * to boot correctly. However, there are very few registers where this 370 * is not true and some values need to be recreated. 371 */ 372 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 373 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 374 375 /* 376 * These bits are set in the gicv3 driver. Losing them (especially the 377 * SRE bit) is problematic for all worlds. Henceforth recreate them. 378 */ 379 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 380 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 381 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 382 383 /* 384 * The actlr_el2 register can be initialized in platform's reset handler 385 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 386 */ 387 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 388 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 389 390 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 391 scr_el3 = SCR_RESET_VAL; 392 393 /* 394 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 395 * EL2, EL1 and EL0 are not trapped to EL3. 396 * 397 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 398 * EL2, EL1 and EL0 are not trapped to EL3. 399 * 400 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 401 * both Security states and both Execution states. 402 * 403 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 404 * Non-secure memory. 405 */ 406 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 407 408 scr_el3 |= SCR_SIF_BIT; 409 410 /* 411 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 412 * Exception level as specified by SPSR. 413 */ 414 if (GET_RW(ep->spsr) == MODE_RW_64) { 415 scr_el3 |= SCR_RW_BIT; 416 } 417 418 /* 419 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 420 * Secure timer registers to EL3, from AArch64 state only, if specified 421 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 422 * bit always behaves as 1 (i.e. secure physical timer register access 423 * is not trapped) 424 */ 425 if (EP_GET_ST(ep->h.attr) != 0U) { 426 scr_el3 |= SCR_ST_BIT; 427 } 428 429 /* 430 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 431 * SCR_EL3.HXEn. 432 */ 433 if (is_feat_hcx_supported()) { 434 scr_el3 |= SCR_HXEn_BIT; 435 } 436 437 /* 438 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 439 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 440 * SCR_EL3.EnAS0. 441 */ 442 if (is_feat_ls64_accdata_supported()) { 443 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 444 } 445 446 /* 447 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 448 * registers are trapped to EL3. 449 */ 450 #if ENABLE_FEAT_RNG_TRAP 451 scr_el3 |= SCR_TRNDR_BIT; 452 #endif 453 454 #if FAULT_INJECTION_SUPPORT 455 /* Enable fault injection from lower ELs */ 456 scr_el3 |= SCR_FIEN_BIT; 457 #endif 458 459 #if CTX_INCLUDE_PAUTH_REGS 460 /* 461 * Enable Pointer Authentication globally for all the worlds. 462 * 463 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 464 * other than EL3 465 * 466 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 467 * than EL3 468 */ 469 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 470 #endif /* CTX_INCLUDE_PAUTH_REGS */ 471 472 /* 473 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 474 */ 475 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 476 scr_el3 |= SCR_TCR2EN_BIT; 477 } 478 479 /* 480 * SCR_EL3.PIEN: Enable permission indirection and overlay 481 * registers for AArch64 if present. 482 */ 483 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 484 scr_el3 |= SCR_PIEN_BIT; 485 } 486 487 /* 488 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 489 */ 490 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 491 scr_el3 |= SCR_GCSEn_BIT; 492 } 493 494 /* 495 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 496 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 497 * next mode is Hyp. 498 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 499 * same conditions as HVC instructions and when the processor supports 500 * ARMv8.6-FGT. 501 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 502 * CNTPOFF_EL2 register under the same conditions as HVC instructions 503 * and when the processor supports ECV. 504 */ 505 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 506 || ((GET_RW(ep->spsr) != MODE_RW_64) 507 && (GET_M32(ep->spsr) == MODE32_hyp))) { 508 scr_el3 |= SCR_HCE_BIT; 509 510 if (is_feat_fgt_supported()) { 511 scr_el3 |= SCR_FGTEN_BIT; 512 } 513 514 if (is_feat_ecv_supported()) { 515 scr_el3 |= SCR_ECVEN_BIT; 516 } 517 } 518 519 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 520 if (is_feat_twed_supported()) { 521 /* Set delay in SCR_EL3 */ 522 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 523 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 524 << SCR_TWEDEL_SHIFT); 525 526 /* Enable WFE delay */ 527 scr_el3 |= SCR_TWEDEn_BIT; 528 } 529 530 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 531 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 532 if (is_feat_sel2_supported()) { 533 scr_el3 |= SCR_EEL2_BIT; 534 } 535 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 536 537 /* 538 * Populate EL3 state so that we've the right context 539 * before doing ERET 540 */ 541 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 542 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 543 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 544 545 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 546 mdcr_el3 = MDCR_EL3_RESET_VAL; 547 548 /* --------------------------------------------------------------------- 549 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 550 * Some fields are architecturally UNKNOWN on reset. 551 * 552 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 553 * Debug exceptions, other than Breakpoint Instruction exceptions, are 554 * disabled from all ELs in Secure state. 555 * 556 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 557 * privileged debug from S-EL1. 558 * 559 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 560 * access to the powerdown debug registers do not trap to EL3. 561 * 562 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 563 * debug registers, other than those registers that are controlled by 564 * MDCR_EL3.TDOSA. 565 */ 566 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 567 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 568 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 569 570 /* 571 * Configure MDCR_EL3 register as applicable for each world 572 * (NS/Secure/Realm) context. 573 */ 574 manage_extensions_common(ctx); 575 576 /* 577 * Store the X0-X7 value from the entrypoint into the context 578 * Use memcpy as we are in control of the layout of the structures 579 */ 580 gp_regs = get_gpregs_ctx(ctx); 581 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 582 } 583 584 /******************************************************************************* 585 * Context management library initialization routine. This library is used by 586 * runtime services to share pointers to 'cpu_context' structures for secure 587 * non-secure and realm states. Management of the structures and their associated 588 * memory is not done by the context management library e.g. the PSCI service 589 * manages the cpu context used for entry from and exit to the non-secure state. 590 * The Secure payload dispatcher service manages the context(s) corresponding to 591 * the secure state. It also uses this library to get access to the non-secure 592 * state cpu context pointers. 593 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 594 * which will be used for programming an entry into a lower EL. The same context 595 * will be used to save state upon exception entry from that EL. 596 ******************************************************************************/ 597 void __init cm_init(void) 598 { 599 /* 600 * The context management library has only global data to initialize, but 601 * that will be done when the BSS is zeroed out. 602 */ 603 } 604 605 /******************************************************************************* 606 * This is the high-level function used to initialize the cpu_context 'ctx' for 607 * first use. It performs initializations that are common to all security states 608 * and initializations specific to the security state specified in 'ep' 609 ******************************************************************************/ 610 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 611 { 612 unsigned int security_state; 613 614 assert(ctx != NULL); 615 616 /* 617 * Perform initializations that are common 618 * to all security states 619 */ 620 setup_context_common(ctx, ep); 621 622 security_state = GET_SECURITY_STATE(ep->h.attr); 623 624 /* Perform security state specific initializations */ 625 switch (security_state) { 626 case SECURE: 627 setup_secure_context(ctx, ep); 628 break; 629 #if ENABLE_RME 630 case REALM: 631 setup_realm_context(ctx, ep); 632 break; 633 #endif 634 case NON_SECURE: 635 setup_ns_context(ctx, ep); 636 break; 637 default: 638 ERROR("Invalid security state\n"); 639 panic(); 640 break; 641 } 642 } 643 644 /******************************************************************************* 645 * Enable architecture extensions for EL3 execution. This function only updates 646 * registers in-place which are expected to either never change or be 647 * overwritten by el3_exit. 648 ******************************************************************************/ 649 #if IMAGE_BL31 650 void cm_manage_extensions_el3(void) 651 { 652 if (is_feat_amu_supported()) { 653 amu_init_el3(); 654 } 655 656 if (is_feat_sme_supported()) { 657 sme_init_el3(); 658 } 659 660 pmuv3_init_el3(); 661 } 662 #endif /* IMAGE_BL31 */ 663 664 /****************************************************************************** 665 * Function to initialise the registers with the RESET values in the context 666 * memory, which are maintained per world. 667 ******************************************************************************/ 668 #if IMAGE_BL31 669 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 670 { 671 /* 672 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 673 * 674 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 675 * by Advanced SIMD, floating-point or SVE instructions (if 676 * implemented) do not trap to EL3. 677 * 678 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 679 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 680 */ 681 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 682 683 per_world_ctx->ctx_cptr_el3 = cptr_el3; 684 685 /* 686 * Initialize MPAM3_EL3 to its default reset value 687 * 688 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 689 * all lower ELn MPAM3_EL3 register access to, trap to EL3 690 */ 691 692 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 693 } 694 #endif /* IMAGE_BL31 */ 695 696 /******************************************************************************* 697 * Initialise per_world_context for Non-Secure world. 698 * This function enables the architecture extensions, which have same value 699 * across the cores for the non-secure world. 700 ******************************************************************************/ 701 #if IMAGE_BL31 702 void manage_extensions_nonsecure_per_world(void) 703 { 704 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 705 706 if (is_feat_sme_supported()) { 707 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 708 } 709 710 if (is_feat_sve_supported()) { 711 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 712 } 713 714 if (is_feat_amu_supported()) { 715 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 716 } 717 718 if (is_feat_sys_reg_trace_supported()) { 719 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 720 } 721 722 if (is_feat_mpam_supported()) { 723 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 724 } 725 726 if (is_feat_fpmr_supported()) { 727 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 728 } 729 } 730 #endif /* IMAGE_BL31 */ 731 732 /******************************************************************************* 733 * Initialise per_world_context for Secure world. 734 * This function enables the architecture extensions, which have same value 735 * across the cores for the secure world. 736 ******************************************************************************/ 737 static void manage_extensions_secure_per_world(void) 738 { 739 #if IMAGE_BL31 740 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 741 742 if (is_feat_sme_supported()) { 743 744 if (ENABLE_SME_FOR_SWD) { 745 /* 746 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 747 * SME, SVE, and FPU/SIMD context properly managed. 748 */ 749 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 750 } else { 751 /* 752 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 753 * world can safely use the associated registers. 754 */ 755 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 756 } 757 } 758 if (is_feat_sve_supported()) { 759 if (ENABLE_SVE_FOR_SWD) { 760 /* 761 * Enable SVE and FPU in secure context, SPM must ensure 762 * that the SVE and FPU register contexts are properly managed. 763 */ 764 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 765 } else { 766 /* 767 * Disable SVE and FPU in secure context so non-secure world 768 * can safely use them. 769 */ 770 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 771 } 772 } 773 774 /* NS can access this but Secure shouldn't */ 775 if (is_feat_sys_reg_trace_supported()) { 776 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 777 } 778 779 has_secure_perworld_init = true; 780 #endif /* IMAGE_BL31 */ 781 } 782 783 /******************************************************************************* 784 * Enable architecture extensions on first entry to Non-secure world only 785 * and disable for secure world. 786 * 787 * NOTE: Arch features which have been provided with the capability of getting 788 * enabled only for non-secure world and being disabled for secure world are 789 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 790 ******************************************************************************/ 791 static void manage_extensions_common(cpu_context_t *ctx) 792 { 793 #if IMAGE_BL31 794 if (is_feat_spe_supported()) { 795 /* 796 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 797 */ 798 spe_enable(ctx); 799 } 800 801 if (is_feat_trbe_supported()) { 802 /* 803 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 804 * Realm state. 805 */ 806 trbe_enable(ctx); 807 } 808 809 if (is_feat_trf_supported()) { 810 /* 811 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 812 */ 813 trf_enable(ctx); 814 } 815 #endif /* IMAGE_BL31 */ 816 } 817 818 /******************************************************************************* 819 * Enable architecture extensions on first entry to Non-secure world. 820 ******************************************************************************/ 821 static void manage_extensions_nonsecure(cpu_context_t *ctx) 822 { 823 #if IMAGE_BL31 824 if (is_feat_amu_supported()) { 825 amu_enable(ctx); 826 } 827 828 if (is_feat_sme_supported()) { 829 sme_enable(ctx); 830 } 831 832 if (is_feat_fgt2_supported()) { 833 fgt2_enable(ctx); 834 } 835 836 if (is_feat_debugv8p9_supported()) { 837 debugv8p9_extended_bp_wp_enable(ctx); 838 } 839 840 if (is_feat_brbe_supported()) { 841 brbe_enable(ctx); 842 } 843 844 pmuv3_enable(ctx); 845 #endif /* IMAGE_BL31 */ 846 } 847 848 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 849 static __unused void enable_pauth_el2(void) 850 { 851 u_register_t hcr_el2 = read_hcr_el2(); 852 /* 853 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 854 * accessing key registers or using pointer authentication instructions 855 * from lower ELs. 856 */ 857 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 858 859 write_hcr_el2(hcr_el2); 860 } 861 862 #if INIT_UNUSED_NS_EL2 863 /******************************************************************************* 864 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 865 * world when EL2 is empty and unused. 866 ******************************************************************************/ 867 static void manage_extensions_nonsecure_el2_unused(void) 868 { 869 #if IMAGE_BL31 870 if (is_feat_spe_supported()) { 871 spe_init_el2_unused(); 872 } 873 874 if (is_feat_amu_supported()) { 875 amu_init_el2_unused(); 876 } 877 878 if (is_feat_mpam_supported()) { 879 mpam_init_el2_unused(); 880 } 881 882 if (is_feat_trbe_supported()) { 883 trbe_init_el2_unused(); 884 } 885 886 if (is_feat_sys_reg_trace_supported()) { 887 sys_reg_trace_init_el2_unused(); 888 } 889 890 if (is_feat_trf_supported()) { 891 trf_init_el2_unused(); 892 } 893 894 pmuv3_init_el2_unused(); 895 896 if (is_feat_sve_supported()) { 897 sve_init_el2_unused(); 898 } 899 900 if (is_feat_sme_supported()) { 901 sme_init_el2_unused(); 902 } 903 904 #if ENABLE_PAUTH 905 enable_pauth_el2(); 906 #endif /* ENABLE_PAUTH */ 907 #endif /* IMAGE_BL31 */ 908 } 909 #endif /* INIT_UNUSED_NS_EL2 */ 910 911 /******************************************************************************* 912 * Enable architecture extensions on first entry to Secure world. 913 ******************************************************************************/ 914 static void manage_extensions_secure(cpu_context_t *ctx) 915 { 916 #if IMAGE_BL31 917 if (is_feat_sme_supported()) { 918 if (ENABLE_SME_FOR_SWD) { 919 /* 920 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 921 * must ensure SME, SVE, and FPU/SIMD context properly managed. 922 */ 923 sme_init_el3(); 924 sme_enable(ctx); 925 } else { 926 /* 927 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 928 * world can safely use the associated registers. 929 */ 930 sme_disable(ctx); 931 } 932 } 933 #endif /* IMAGE_BL31 */ 934 } 935 936 #if !IMAGE_BL1 937 /******************************************************************************* 938 * The following function initializes the cpu_context for a CPU specified by 939 * its `cpu_idx` for first use, and sets the initial entrypoint state as 940 * specified by the entry_point_info structure. 941 ******************************************************************************/ 942 void cm_init_context_by_index(unsigned int cpu_idx, 943 const entry_point_info_t *ep) 944 { 945 cpu_context_t *ctx; 946 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 947 cm_setup_context(ctx, ep); 948 } 949 #endif /* !IMAGE_BL1 */ 950 951 /******************************************************************************* 952 * The following function initializes the cpu_context for the current CPU 953 * for first use, and sets the initial entrypoint state as specified by the 954 * entry_point_info structure. 955 ******************************************************************************/ 956 void cm_init_my_context(const entry_point_info_t *ep) 957 { 958 cpu_context_t *ctx; 959 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 960 cm_setup_context(ctx, ep); 961 } 962 963 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 964 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 965 { 966 #if INIT_UNUSED_NS_EL2 967 u_register_t hcr_el2 = HCR_RESET_VAL; 968 u_register_t mdcr_el2; 969 u_register_t scr_el3; 970 971 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 972 973 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 974 if ((scr_el3 & SCR_RW_BIT) != 0U) { 975 hcr_el2 |= HCR_RW_BIT; 976 } 977 978 write_hcr_el2(hcr_el2); 979 980 /* 981 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 982 * All fields have architecturally UNKNOWN reset values. 983 */ 984 write_cptr_el2(CPTR_EL2_RESET_VAL); 985 986 /* 987 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 988 * reset and are set to zero except for field(s) listed below. 989 * 990 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 991 * Non-secure EL0 and EL1 accesses to the physical timer registers. 992 * 993 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 994 * Non-secure EL0 and EL1 accesses to the physical counter registers. 995 */ 996 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 997 998 /* 999 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1000 * UNKNOWN value. 1001 */ 1002 write_cntvoff_el2(0); 1003 1004 /* 1005 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1006 * respectively. 1007 */ 1008 write_vpidr_el2(read_midr_el1()); 1009 write_vmpidr_el2(read_mpidr_el1()); 1010 1011 /* 1012 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1013 * 1014 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1015 * translation is disabled, cache maintenance operations depend on the 1016 * VMID. 1017 * 1018 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1019 * disabled. 1020 */ 1021 write_vttbr_el2(VTTBR_RESET_VAL & 1022 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1023 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1024 1025 /* 1026 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1027 * Some fields are architecturally UNKNOWN on reset. 1028 * 1029 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1030 * register accesses to the Debug ROM registers are not trapped to EL2. 1031 * 1032 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1033 * accesses to the powerdown debug registers are not trapped to EL2. 1034 * 1035 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1036 * debug registers do not trap to EL2. 1037 * 1038 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1039 * EL2. 1040 */ 1041 mdcr_el2 = MDCR_EL2_RESET_VAL & 1042 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1043 MDCR_EL2_TDE_BIT); 1044 1045 write_mdcr_el2(mdcr_el2); 1046 1047 /* 1048 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1049 * 1050 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1051 * EL1 accesses to System registers do not trap to EL2. 1052 */ 1053 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1054 1055 /* 1056 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1057 * reset. 1058 * 1059 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1060 * and prevent timer interrupts. 1061 */ 1062 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1063 1064 manage_extensions_nonsecure_el2_unused(); 1065 #endif /* INIT_UNUSED_NS_EL2 */ 1066 } 1067 1068 /******************************************************************************* 1069 * Prepare the CPU system registers for first entry into realm, secure, or 1070 * normal world. 1071 * 1072 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1073 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1074 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1075 * For all entries, the EL1 registers are initialized from the cpu_context 1076 ******************************************************************************/ 1077 void cm_prepare_el3_exit(uint32_t security_state) 1078 { 1079 u_register_t sctlr_el2, scr_el3; 1080 cpu_context_t *ctx = cm_get_context(security_state); 1081 1082 assert(ctx != NULL); 1083 1084 if (security_state == NON_SECURE) { 1085 uint64_t el2_implemented = el_implemented(2); 1086 1087 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1088 CTX_SCR_EL3); 1089 1090 if (el2_implemented != EL_IMPL_NONE) { 1091 1092 /* 1093 * If context is not being used for EL2, initialize 1094 * HCRX_EL2 with its init value here. 1095 */ 1096 if (is_feat_hcx_supported()) { 1097 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1098 } 1099 1100 /* 1101 * Initialize Fine-grained trap registers introduced 1102 * by FEAT_FGT so all traps are initially disabled when 1103 * switching to EL2 or a lower EL, preventing undesired 1104 * behavior. 1105 */ 1106 if (is_feat_fgt_supported()) { 1107 /* 1108 * Initialize HFG*_EL2 registers with a default 1109 * value so legacy systems unaware of FEAT_FGT 1110 * do not get trapped due to their lack of 1111 * initialization for this feature. 1112 */ 1113 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1114 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1115 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1116 } 1117 1118 /* Condition to ensure EL2 is being used. */ 1119 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1120 /* Initialize SCTLR_EL2 register with reset value. */ 1121 sctlr_el2 = SCTLR_EL2_RES1; 1122 1123 /* 1124 * If workaround of errata 764081 for Cortex-A75 1125 * is used then set SCTLR_EL2.IESB to enable 1126 * Implicit Error Synchronization Barrier. 1127 */ 1128 if (errata_a75_764081_applies()) { 1129 sctlr_el2 |= SCTLR_IESB_BIT; 1130 } 1131 1132 write_sctlr_el2(sctlr_el2); 1133 } else { 1134 /* 1135 * (scr_el3 & SCR_HCE_BIT==0) 1136 * EL2 implemented but unused. 1137 */ 1138 init_nonsecure_el2_unused(ctx); 1139 } 1140 } 1141 } 1142 #if (!CTX_INCLUDE_EL2_REGS) 1143 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1144 cm_el1_sysregs_context_restore(security_state); 1145 #endif 1146 cm_set_next_eret_context(security_state); 1147 } 1148 1149 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1150 1151 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1152 { 1153 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1154 if (is_feat_amu_supported()) { 1155 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1156 } 1157 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1158 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1159 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1160 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1161 } 1162 1163 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1164 { 1165 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1166 if (is_feat_amu_supported()) { 1167 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1168 } 1169 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1170 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1171 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1172 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1173 } 1174 1175 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1176 { 1177 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1178 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1179 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1180 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1181 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1182 } 1183 1184 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1185 { 1186 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1187 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1188 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1189 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1190 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1191 } 1192 1193 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1194 { 1195 u_register_t mpam_idr = read_mpamidr_el1(); 1196 1197 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1198 1199 /* 1200 * The context registers that we intend to save would be part of the 1201 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1202 */ 1203 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1204 return; 1205 } 1206 1207 /* 1208 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1209 * MPAMIDR_HAS_HCR_BIT == 1. 1210 */ 1211 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1212 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1213 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1214 1215 /* 1216 * The number of MPAMVPM registers is implementation defined, their 1217 * number is stored in the MPAMIDR_EL1 register. 1218 */ 1219 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1220 case 7: 1221 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1222 __fallthrough; 1223 case 6: 1224 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1225 __fallthrough; 1226 case 5: 1227 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1228 __fallthrough; 1229 case 4: 1230 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1231 __fallthrough; 1232 case 3: 1233 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1234 __fallthrough; 1235 case 2: 1236 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1237 __fallthrough; 1238 case 1: 1239 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1240 break; 1241 } 1242 } 1243 1244 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1245 { 1246 u_register_t mpam_idr = read_mpamidr_el1(); 1247 1248 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1249 1250 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1251 return; 1252 } 1253 1254 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1255 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1256 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1257 1258 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1259 case 7: 1260 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1261 __fallthrough; 1262 case 6: 1263 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1264 __fallthrough; 1265 case 5: 1266 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1267 __fallthrough; 1268 case 4: 1269 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1270 __fallthrough; 1271 case 3: 1272 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1273 __fallthrough; 1274 case 2: 1275 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1276 __fallthrough; 1277 case 1: 1278 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1279 break; 1280 } 1281 } 1282 1283 /* --------------------------------------------------------------------------- 1284 * The following registers are not added: 1285 * ICH_AP0R<n>_EL2 1286 * ICH_AP1R<n>_EL2 1287 * ICH_LR<n>_EL2 1288 * 1289 * NOTE: For a system with S-EL2 present but not enabled, accessing 1290 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1291 * SCR_EL3.NS = 1 before accessing this register. 1292 * --------------------------------------------------------------------------- 1293 */ 1294 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1295 { 1296 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1297 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1298 #else 1299 u_register_t scr_el3 = read_scr_el3(); 1300 write_scr_el3(scr_el3 | SCR_NS_BIT); 1301 isb(); 1302 1303 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1304 1305 write_scr_el3(scr_el3); 1306 isb(); 1307 #endif 1308 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1309 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1310 } 1311 1312 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1313 { 1314 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1315 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1316 #else 1317 u_register_t scr_el3 = read_scr_el3(); 1318 write_scr_el3(scr_el3 | SCR_NS_BIT); 1319 isb(); 1320 1321 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1322 1323 write_scr_el3(scr_el3); 1324 isb(); 1325 #endif 1326 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1327 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1328 } 1329 1330 /* ----------------------------------------------------- 1331 * The following registers are not added: 1332 * AMEVCNTVOFF0<n>_EL2 1333 * AMEVCNTVOFF1<n>_EL2 1334 * ----------------------------------------------------- 1335 */ 1336 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1337 { 1338 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1339 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1340 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1341 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1342 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1343 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1344 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1345 if (CTX_INCLUDE_AARCH32_REGS) { 1346 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1347 } 1348 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1349 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1350 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1351 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1352 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1353 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1354 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1355 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1356 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1357 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1358 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1359 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1360 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1361 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1362 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1363 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1364 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1365 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1366 1367 write_el2_ctx_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1368 write_el2_ctx_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1369 } 1370 1371 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1372 { 1373 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1374 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1375 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1376 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1377 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1378 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1379 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1380 if (CTX_INCLUDE_AARCH32_REGS) { 1381 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1382 } 1383 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1384 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1385 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1386 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1387 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1388 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1389 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1390 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1391 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1392 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1393 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1394 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1395 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1396 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1397 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1398 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1399 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1400 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1401 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1402 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1403 } 1404 1405 /******************************************************************************* 1406 * Save EL2 sysreg context 1407 ******************************************************************************/ 1408 void cm_el2_sysregs_context_save(uint32_t security_state) 1409 { 1410 cpu_context_t *ctx; 1411 el2_sysregs_t *el2_sysregs_ctx; 1412 1413 ctx = cm_get_context(security_state); 1414 assert(ctx != NULL); 1415 1416 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1417 1418 el2_sysregs_context_save_common(el2_sysregs_ctx); 1419 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1420 1421 if (is_feat_mte2_supported()) { 1422 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1423 } 1424 1425 if (is_feat_mpam_supported()) { 1426 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1427 } 1428 1429 if (is_feat_fgt_supported()) { 1430 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1431 } 1432 1433 if (is_feat_fgt2_supported()) { 1434 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1435 } 1436 1437 if (is_feat_ecv_v2_supported()) { 1438 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1439 } 1440 1441 if (is_feat_vhe_supported()) { 1442 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1443 read_contextidr_el2()); 1444 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1445 } 1446 1447 if (is_feat_ras_supported()) { 1448 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1449 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1450 } 1451 1452 if (is_feat_nv2_supported()) { 1453 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1454 } 1455 1456 if (is_feat_trf_supported()) { 1457 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1458 } 1459 1460 if (is_feat_csv2_2_supported()) { 1461 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1462 read_scxtnum_el2()); 1463 } 1464 1465 if (is_feat_hcx_supported()) { 1466 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1467 } 1468 1469 if (is_feat_tcr2_supported()) { 1470 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1471 } 1472 1473 if (is_feat_sxpie_supported()) { 1474 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1475 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1476 } 1477 1478 if (is_feat_sxpoe_supported()) { 1479 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1480 } 1481 1482 if (is_feat_s2pie_supported()) { 1483 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1484 } 1485 1486 if (is_feat_gcs_supported()) { 1487 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1488 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1489 } 1490 1491 if (is_feat_sctlr2_supported()) { 1492 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1493 } 1494 } 1495 1496 /******************************************************************************* 1497 * Restore EL2 sysreg context 1498 ******************************************************************************/ 1499 void cm_el2_sysregs_context_restore(uint32_t security_state) 1500 { 1501 cpu_context_t *ctx; 1502 el2_sysregs_t *el2_sysregs_ctx; 1503 1504 ctx = cm_get_context(security_state); 1505 assert(ctx != NULL); 1506 1507 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1508 1509 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1510 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1511 1512 if (is_feat_mte2_supported()) { 1513 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1514 } 1515 1516 if (is_feat_mpam_supported()) { 1517 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1518 } 1519 1520 if (is_feat_fgt_supported()) { 1521 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1522 } 1523 1524 if (is_feat_fgt2_supported()) { 1525 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1526 } 1527 1528 if (is_feat_ecv_v2_supported()) { 1529 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1530 } 1531 1532 if (is_feat_vhe_supported()) { 1533 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1534 contextidr_el2)); 1535 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1536 } 1537 1538 if (is_feat_ras_supported()) { 1539 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1540 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1541 } 1542 1543 if (is_feat_nv2_supported()) { 1544 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1545 } 1546 1547 if (is_feat_trf_supported()) { 1548 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1549 } 1550 1551 if (is_feat_csv2_2_supported()) { 1552 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1553 scxtnum_el2)); 1554 } 1555 1556 if (is_feat_hcx_supported()) { 1557 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1558 } 1559 1560 if (is_feat_tcr2_supported()) { 1561 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1562 } 1563 1564 if (is_feat_sxpie_supported()) { 1565 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1566 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1567 } 1568 1569 if (is_feat_sxpoe_supported()) { 1570 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1571 } 1572 1573 if (is_feat_s2pie_supported()) { 1574 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1575 } 1576 1577 if (is_feat_gcs_supported()) { 1578 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1579 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1580 } 1581 1582 if (is_feat_sctlr2_supported()) { 1583 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1584 } 1585 } 1586 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1587 1588 #if IMAGE_BL31 1589 /********************************************************************************* 1590 * This function allows Architecture features asymmetry among cores. 1591 * TF-A assumes that all the cores in the platform has architecture feature parity 1592 * and hence the context is setup on different core (e.g. primary sets up the 1593 * context for secondary cores).This assumption may not be true for systems where 1594 * cores are not conforming to same Arch version or there is CPU Erratum which 1595 * requires certain feature to be be disabled only on a given core. 1596 * 1597 * This function is called on secondary cores to override any disparity in context 1598 * setup by primary, this would be called during warmboot path. 1599 *********************************************************************************/ 1600 void cm_handle_asymmetric_features(void) 1601 { 1602 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1603 1604 assert(ctx != NULL); 1605 1606 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1607 if (is_feat_spe_supported()) { 1608 spe_enable(ctx); 1609 } else { 1610 spe_disable(ctx); 1611 } 1612 #endif 1613 1614 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1615 if (check_if_affected_core() == ERRATA_APPLIES) { 1616 if (is_feat_trbe_supported()) { 1617 trbe_disable(ctx); 1618 } 1619 } 1620 #endif 1621 1622 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1623 el3_state_t *el3_state = get_el3state_ctx(ctx); 1624 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1625 1626 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1627 tcr2_enable(ctx); 1628 } else { 1629 tcr2_disable(ctx); 1630 } 1631 #endif 1632 1633 } 1634 #endif 1635 1636 /******************************************************************************* 1637 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1638 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1639 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1640 * cm_prepare_el3_exit function. 1641 ******************************************************************************/ 1642 void cm_prepare_el3_exit_ns(void) 1643 { 1644 #if IMAGE_BL31 1645 /* 1646 * Check and handle Architecture feature asymmetry among cores. 1647 * 1648 * In warmboot path secondary cores context is initialized on core which 1649 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1650 * it in this function call. 1651 * For Symmetric cores this is an empty function. 1652 */ 1653 cm_handle_asymmetric_features(); 1654 #endif 1655 1656 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1657 #if ENABLE_ASSERTIONS 1658 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1659 assert(ctx != NULL); 1660 1661 /* Assert that EL2 is used. */ 1662 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1663 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1664 (el_implemented(2U) != EL_IMPL_NONE)); 1665 #endif /* ENABLE_ASSERTIONS */ 1666 1667 /* Restore EL2 sysreg contexts */ 1668 cm_el2_sysregs_context_restore(NON_SECURE); 1669 cm_set_next_eret_context(NON_SECURE); 1670 #else 1671 cm_prepare_el3_exit(NON_SECURE); 1672 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1673 } 1674 1675 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1676 /******************************************************************************* 1677 * The next set of six functions are used by runtime services to save and restore 1678 * EL1 context on the 'cpu_context' structure for the specified security state. 1679 ******************************************************************************/ 1680 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1681 { 1682 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1683 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1684 1685 #if (!ERRATA_SPECULATIVE_AT) 1686 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1687 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1688 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1689 1690 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1691 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1692 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1693 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1694 write_el1_ctx_common(ctx, ttbr0_el1, read_ttbr0_el1()); 1695 write_el1_ctx_common(ctx, ttbr1_el1, read_ttbr1_el1()); 1696 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1697 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1698 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1699 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1700 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1701 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1702 write_el1_ctx_common(ctx, par_el1, read_par_el1()); 1703 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1704 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1705 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1706 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1707 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1708 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1709 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1710 1711 if (CTX_INCLUDE_AARCH32_REGS) { 1712 /* Save Aarch32 registers */ 1713 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1714 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1715 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1716 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1717 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1718 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1719 } 1720 1721 if (NS_TIMER_SWITCH) { 1722 /* Save NS Timer registers */ 1723 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1724 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1725 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1726 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1727 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1728 } 1729 1730 if (is_feat_mte2_supported()) { 1731 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1732 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1733 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1734 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1735 } 1736 1737 if (is_feat_ras_supported()) { 1738 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1739 } 1740 1741 if (is_feat_s1pie_supported()) { 1742 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1743 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1744 } 1745 1746 if (is_feat_s1poe_supported()) { 1747 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1748 } 1749 1750 if (is_feat_s2poe_supported()) { 1751 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1752 } 1753 1754 if (is_feat_tcr2_supported()) { 1755 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1756 } 1757 1758 if (is_feat_trf_supported()) { 1759 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1760 } 1761 1762 if (is_feat_csv2_2_supported()) { 1763 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1764 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1765 } 1766 1767 if (is_feat_gcs_supported()) { 1768 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1769 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1770 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1771 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1772 } 1773 1774 if (is_feat_the_supported()) { 1775 write_el1_ctx_the(ctx, rcwmask_el1, read_rcwmask_el1()); 1776 write_el1_ctx_the(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1777 } 1778 1779 if (is_feat_sctlr2_supported()) { 1780 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1781 } 1782 1783 if (is_feat_ls64_accdata_supported()) { 1784 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1785 } 1786 } 1787 1788 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1789 { 1790 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1791 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1792 1793 #if (!ERRATA_SPECULATIVE_AT) 1794 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1795 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1796 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1797 1798 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1799 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1800 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1801 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1802 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1803 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1804 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1805 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1806 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1807 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1808 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1809 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1810 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1811 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1812 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1813 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1814 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1815 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1816 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1817 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1818 1819 if (CTX_INCLUDE_AARCH32_REGS) { 1820 /* Restore Aarch32 registers */ 1821 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1822 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1823 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1824 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1825 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1826 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1827 } 1828 1829 if (NS_TIMER_SWITCH) { 1830 /* Restore NS Timer registers */ 1831 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1832 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1833 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1834 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1835 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1836 } 1837 1838 if (is_feat_mte2_supported()) { 1839 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1840 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1841 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1842 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1843 } 1844 1845 if (is_feat_ras_supported()) { 1846 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1847 } 1848 1849 if (is_feat_s1pie_supported()) { 1850 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1851 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1852 } 1853 1854 if (is_feat_s1poe_supported()) { 1855 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1856 } 1857 1858 if (is_feat_s2poe_supported()) { 1859 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1860 } 1861 1862 if (is_feat_tcr2_supported()) { 1863 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1864 } 1865 1866 if (is_feat_trf_supported()) { 1867 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1868 } 1869 1870 if (is_feat_csv2_2_supported()) { 1871 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1872 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1873 } 1874 1875 if (is_feat_gcs_supported()) { 1876 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1877 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1878 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1879 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1880 } 1881 1882 if (is_feat_the_supported()) { 1883 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1884 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1885 } 1886 1887 if (is_feat_sctlr2_supported()) { 1888 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1889 } 1890 1891 if (is_feat_ls64_accdata_supported()) { 1892 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1893 } 1894 } 1895 1896 /******************************************************************************* 1897 * The next couple of functions are used by runtime services to save and restore 1898 * EL1 context on the 'cpu_context' structure for the specified security state. 1899 ******************************************************************************/ 1900 void cm_el1_sysregs_context_save(uint32_t security_state) 1901 { 1902 cpu_context_t *ctx; 1903 1904 ctx = cm_get_context(security_state); 1905 assert(ctx != NULL); 1906 1907 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1908 1909 #if IMAGE_BL31 1910 if (security_state == SECURE) 1911 PUBLISH_EVENT(cm_exited_secure_world); 1912 else 1913 PUBLISH_EVENT(cm_exited_normal_world); 1914 #endif 1915 } 1916 1917 void cm_el1_sysregs_context_restore(uint32_t security_state) 1918 { 1919 cpu_context_t *ctx; 1920 1921 ctx = cm_get_context(security_state); 1922 assert(ctx != NULL); 1923 1924 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1925 1926 #if IMAGE_BL31 1927 if (security_state == SECURE) 1928 PUBLISH_EVENT(cm_entering_secure_world); 1929 else 1930 PUBLISH_EVENT(cm_entering_normal_world); 1931 #endif 1932 } 1933 1934 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1935 1936 /******************************************************************************* 1937 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1938 * given security state with the given entrypoint 1939 ******************************************************************************/ 1940 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1941 { 1942 cpu_context_t *ctx; 1943 el3_state_t *state; 1944 1945 ctx = cm_get_context(security_state); 1946 assert(ctx != NULL); 1947 1948 /* Populate EL3 state so that ERET jumps to the correct entry */ 1949 state = get_el3state_ctx(ctx); 1950 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1951 } 1952 1953 /******************************************************************************* 1954 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1955 * pertaining to the given security state 1956 ******************************************************************************/ 1957 void cm_set_elr_spsr_el3(uint32_t security_state, 1958 uintptr_t entrypoint, uint32_t spsr) 1959 { 1960 cpu_context_t *ctx; 1961 el3_state_t *state; 1962 1963 ctx = cm_get_context(security_state); 1964 assert(ctx != NULL); 1965 1966 /* Populate EL3 state so that ERET jumps to the correct entry */ 1967 state = get_el3state_ctx(ctx); 1968 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1969 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1970 } 1971 1972 /******************************************************************************* 1973 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1974 * pertaining to the given security state using the value and bit position 1975 * specified in the parameters. It preserves all other bits. 1976 ******************************************************************************/ 1977 void cm_write_scr_el3_bit(uint32_t security_state, 1978 uint32_t bit_pos, 1979 uint32_t value) 1980 { 1981 cpu_context_t *ctx; 1982 el3_state_t *state; 1983 u_register_t scr_el3; 1984 1985 ctx = cm_get_context(security_state); 1986 assert(ctx != NULL); 1987 1988 /* Ensure that the bit position is a valid one */ 1989 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1990 1991 /* Ensure that the 'value' is only a bit wide */ 1992 assert(value <= 1U); 1993 1994 /* 1995 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1996 * and set it to its new value. 1997 */ 1998 state = get_el3state_ctx(ctx); 1999 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2000 scr_el3 &= ~(1UL << bit_pos); 2001 scr_el3 |= (u_register_t)value << bit_pos; 2002 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2003 } 2004 2005 /******************************************************************************* 2006 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2007 * given security state. 2008 ******************************************************************************/ 2009 u_register_t cm_get_scr_el3(uint32_t security_state) 2010 { 2011 cpu_context_t *ctx; 2012 el3_state_t *state; 2013 2014 ctx = cm_get_context(security_state); 2015 assert(ctx != NULL); 2016 2017 /* Populate EL3 state so that ERET jumps to the correct entry */ 2018 state = get_el3state_ctx(ctx); 2019 return read_ctx_reg(state, CTX_SCR_EL3); 2020 } 2021 2022 /******************************************************************************* 2023 * This function is used to program the context that's used for exception 2024 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2025 * the required security state 2026 ******************************************************************************/ 2027 void cm_set_next_eret_context(uint32_t security_state) 2028 { 2029 cpu_context_t *ctx; 2030 2031 ctx = cm_get_context(security_state); 2032 assert(ctx != NULL); 2033 2034 cm_set_next_context(ctx); 2035 } 2036