1 /* 2 * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_features.h> 8 #include <common/debug.h> 9 #include <common/feat_detect.h> 10 11 static bool tainted; 12 13 /******************************************************************************* 14 * This section lists the wrapper modules for each feature to evaluate the 15 * feature states (FEAT_STATE_ALWAYS and FEAT_STATE_CHECK) and perform 16 * necessary action as below: 17 * 18 * It verifies whether the FEAT_XXX (eg: FEAT_SB) is supported by the PE or not. 19 * Without this check an exception would occur during context save/restore 20 * routines, if the feature is enabled but not supported by PE. 21 ******************************************************************************/ 22 23 #define feat_detect_panic(a, b) ((a) ? (void)0 : feature_panic(b)) 24 25 /******************************************************************************* 26 * Function : feature_panic 27 * Customised panic function with error logging mechanism to list the feature 28 * not supported by the PE. 29 ******************************************************************************/ 30 static inline void feature_panic(char *feat_name) 31 { 32 ERROR("FEAT_%s not supported by the PE\n", feat_name); 33 panic(); 34 } 35 36 /******************************************************************************* 37 * Function : check_feature 38 * Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and 39 * feature availability on the hardware. <min> is the smallest feature 40 * ID field value that is required for that feature. 41 * Triggers a panic later if a feature is forcefully enabled, but not 42 * available on the PE. Also will panic if the hardware feature ID field 43 * is larger than the maximum known and supported number, specified by <max>. 44 * 45 * We force inlining here to let the compiler optimise away the whole check 46 * if the feature is disabled at build time (FEAT_STATE_DISABLED). 47 ******************************************************************************/ 48 static inline void __attribute((__always_inline__)) 49 check_feature(int state, unsigned long field, const char *feat_name, 50 unsigned int min, unsigned int max) 51 { 52 if (state == FEAT_STATE_ALWAYS && field < min) { 53 ERROR("FEAT_%s not supported by the PE\n", feat_name); 54 tainted = true; 55 } 56 if (state >= FEAT_STATE_ALWAYS && field > max) { 57 ERROR("FEAT_%s is version %ld, but is only known up to version %d\n", 58 feat_name, field, max); 59 tainted = true; 60 } 61 } 62 63 /************************************************ 64 * Feature : FEAT_PAUTH (Pointer Authentication) 65 ***********************************************/ 66 static void read_feat_pauth(void) 67 { 68 #if (ENABLE_PAUTH == FEAT_STATE_ALWAYS) || (CTX_INCLUDE_PAUTH_REGS == FEAT_STATE_ALWAYS) 69 feat_detect_panic(is_armv8_3_pauth_present(), "PAUTH"); 70 #endif 71 } 72 73 static unsigned int read_feat_rng_trap_id_field(void) 74 { 75 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 76 ID_AA64PFR1_EL1_RNDR_TRAP_MASK); 77 } 78 79 static unsigned int read_feat_bti_id_field(void) 80 { 81 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT, 82 ID_AA64PFR1_EL1_BT_MASK); 83 } 84 85 static unsigned int read_feat_sb_id_field(void) 86 { 87 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT, 88 ID_AA64ISAR1_SB_MASK); 89 } 90 91 static unsigned int read_feat_csv2_id_field(void) 92 { 93 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT, 94 ID_AA64PFR0_CSV2_MASK); 95 } 96 97 static unsigned int read_feat_debugv8p9_id_field(void) 98 { 99 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_DEBUGVER_SHIFT, 100 ID_AA64DFR0_DEBUGVER_MASK); 101 } 102 103 static unsigned int read_feat_pmuv3_id_field(void) 104 { 105 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT, 106 ID_AA64DFR0_PMUVER_MASK); 107 } 108 109 static unsigned int read_feat_vhe_id_field(void) 110 { 111 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT, 112 ID_AA64MMFR1_EL1_VHE_MASK); 113 } 114 115 static unsigned int read_feat_sve_id_field(void) 116 { 117 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT, 118 ID_AA64PFR0_SVE_MASK); 119 } 120 121 static unsigned int read_feat_ras_id_field(void) 122 { 123 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT, 124 ID_AA64PFR0_RAS_MASK); 125 } 126 127 static unsigned int read_feat_dit_id_field(void) 128 { 129 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT, 130 ID_AA64PFR0_DIT_MASK); 131 } 132 133 static unsigned int read_feat_amu_id_field(void) 134 { 135 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT, 136 ID_AA64PFR0_AMU_MASK); 137 } 138 139 static unsigned int read_feat_mpam_version(void) 140 { 141 return (unsigned int)((((read_id_aa64pfr0_el1() >> 142 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 143 ((read_id_aa64pfr1_el1() >> 144 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); 145 } 146 147 static unsigned int read_feat_nv_id_field(void) 148 { 149 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT, 150 ID_AA64MMFR2_EL1_NV_MASK); 151 } 152 153 static unsigned int read_feat_sel2_id_field(void) 154 { 155 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT, 156 ID_AA64PFR0_SEL2_MASK); 157 } 158 159 static unsigned int read_feat_trf_id_field(void) 160 { 161 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT, 162 ID_AA64DFR0_TRACEFILT_MASK); 163 } 164 static unsigned int get_armv8_5_mte_support(void) 165 { 166 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT, 167 ID_AA64PFR1_EL1_MTE_MASK); 168 } 169 static unsigned int read_feat_rng_id_field(void) 170 { 171 return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT, 172 ID_AA64ISAR0_RNDR_MASK); 173 } 174 static unsigned int read_feat_fgt_id_field(void) 175 { 176 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT, 177 ID_AA64MMFR0_EL1_FGT_MASK); 178 } 179 static unsigned int read_feat_ecv_id_field(void) 180 { 181 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT, 182 ID_AA64MMFR0_EL1_ECV_MASK); 183 } 184 static unsigned int read_feat_twed_id_field(void) 185 { 186 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT, 187 ID_AA64MMFR1_EL1_TWED_MASK); 188 } 189 190 static unsigned int read_feat_hcx_id_field(void) 191 { 192 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT, 193 ID_AA64MMFR1_EL1_HCX_MASK); 194 } 195 static unsigned int read_feat_ls64_id_field(void) 196 { 197 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_LS64_SHIFT, 198 ID_AA64ISAR1_LS64_MASK); 199 } 200 static unsigned int read_feat_tcr2_id_field(void) 201 { 202 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT, 203 ID_AA64MMFR3_EL1_TCRX_MASK); 204 } 205 static unsigned int read_feat_s2pie_id_field(void) 206 { 207 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT, 208 ID_AA64MMFR3_EL1_S2PIE_MASK); 209 } 210 static unsigned int read_feat_s1pie_id_field(void) 211 { 212 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT, 213 ID_AA64MMFR3_EL1_S1PIE_MASK); 214 } 215 static unsigned int read_feat_s2poe_id_field(void) 216 { 217 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT, 218 ID_AA64MMFR3_EL1_S2POE_MASK); 219 } 220 static unsigned int read_feat_s1poe_id_field(void) 221 { 222 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT, 223 ID_AA64MMFR3_EL1_S1POE_MASK); 224 } 225 static unsigned int read_feat_brbe_id_field(void) 226 { 227 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT, 228 ID_AA64DFR0_BRBE_MASK); 229 } 230 static unsigned int read_feat_trbe_id_field(void) 231 { 232 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT, 233 ID_AA64DFR0_TRACEBUFFER_MASK); 234 } 235 static unsigned int read_feat_sme_id_field(void) 236 { 237 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT, 238 ID_AA64PFR1_EL1_SME_MASK); 239 } 240 static unsigned int read_feat_gcs_id_field(void) 241 { 242 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT, 243 ID_AA64PFR1_EL1_GCS_MASK); 244 } 245 246 static unsigned int read_feat_rme_id_field(void) 247 { 248 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT, 249 ID_AA64PFR0_FEAT_RME_MASK); 250 } 251 252 static unsigned int read_feat_pan_id_field(void) 253 { 254 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT, 255 ID_AA64MMFR1_EL1_PAN_MASK); 256 } 257 258 static unsigned int read_feat_mtpmu_id_field(void) 259 { 260 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 261 ID_AA64DFR0_MTPMU_MASK); 262 263 } 264 265 static unsigned int read_feat_the_id_field(void) 266 { 267 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_THE_SHIFT, 268 ID_AA64PFR1_EL1_THE_MASK); 269 } 270 271 static unsigned int read_feat_sctlr2_id_field(void) 272 { 273 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_SCTLR2_SHIFT, 274 ID_AA64MMFR3_EL1_SCTLR2_MASK); 275 } 276 277 static unsigned int read_feat_d128_id_field(void) 278 { 279 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT, 280 ID_AA64MMFR3_EL1_D128_MASK); 281 } 282 283 static unsigned int read_feat_fpmr_id_field(void) 284 { 285 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_FPMR_SHIFT, 286 ID_AA64PFR2_EL1_FPMR_MASK); 287 } 288 289 /*********************************************************************************** 290 * TF-A supports many Arm architectural features starting from arch version 291 * (8.0 till 8.7+). These features are mostly enabled through build flags. This 292 * mechanism helps in validating these build flags in the early boot phase 293 * either in BL1 or BL31 depending on the platform and assists in identifying 294 * and notifying the features which are enabled but not supported by the PE. 295 * 296 * It reads all the enabled features ID-registers and ensures the features 297 * are supported by the PE. 298 * In case if they aren't it stops booting at an early phase and logs the error 299 * messages, notifying the platforms about the features that are not supported. 300 * 301 * Further the procedure is implemented with a tri-state approach for each feature: 302 * ENABLE_FEAT_xxx = 0 : The feature is disabled statically at compile time 303 * ENABLE_FEAT_xxx = 1 : The feature is enabled and must be present in hardware. 304 * There will be panic if feature is not present at cold boot. 305 * ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime 306 * depending on hardware capability. 307 * 308 * For better readability, state values are defined with macros, namely: 309 * { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values 310 * { 0, 1, 2 }, respectively, as their naming. 311 **********************************************************************************/ 312 void detect_arch_features(void) 313 { 314 tainted = false; 315 316 /* v8.0 features */ 317 check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB", 1, 1); 318 check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(), 319 "CSV2_2", 2, 3); 320 /* 321 * Even though the PMUv3 is an OPTIONAL feature, it is always 322 * implemented and Arm prescribes so. So assume it will be there and do 323 * away with a flag for it. This is used to check minor PMUv3px 324 * revisions so that we catch them as they come along 325 */ 326 check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(), 327 "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P8); 328 329 /* v8.1 features */ 330 check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3); 331 check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), "VHE", 1, 1); 332 333 /* v8.2 features */ 334 check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(), 335 "SVE", 1, 1); 336 check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), "RAS", 1, 2); 337 338 /* v8.3 features */ 339 /* TODO: Pauth yet to convert to tri-state feat detect logic */ 340 read_feat_pauth(); 341 342 /* v8.4 features */ 343 check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), "DIT", 1, 1); 344 check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(), 345 "AMUv1", 1, 2); 346 check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(), 347 "MPAM", 1, 17); 348 check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(), 349 "NV2", 2, 2); 350 check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(), 351 "SEL2", 1, 1); 352 check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(), 353 "TRF", 1, 1); 354 355 /* v8.5 features */ 356 check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), "MTE2", 357 MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY); 358 check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), "RNG", 1, 1); 359 check_feature(ENABLE_BTI, read_feat_bti_id_field(), "BTI", 1, 1); 360 check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(), 361 "RNG_TRAP", 1, 1); 362 363 /* v8.6 features */ 364 check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(), 365 "AMUv1p1", 2, 2); 366 check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT", 1, 2); 367 check_feature(ENABLE_FEAT_FGT2, read_feat_fgt_id_field(), "FGT2", 2, 2); 368 check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), "ECV", 1, 2); 369 check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(), 370 "TWED", 1, 1); 371 372 /* 373 * even though this is a "DISABLE" it does confusingly perform feature 374 * enablement duties like all other flags here. Check it against the HW 375 * feature when we intend to diverge from the default behaviour 376 */ 377 check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), "MTPMU", 1, 1); 378 379 /* v8.7 features */ 380 check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1); 381 check_feature(ENABLE_FEAT_LS64_ACCDATA, read_feat_ls64_id_field(), "LS64", 1, 3); 382 383 /* v8.9 features */ 384 check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(), 385 "TCR2", 1, 1); 386 check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(), 387 "S2PIE", 1, 1); 388 check_feature(ENABLE_FEAT_S1PIE, read_feat_s1pie_id_field(), 389 "S1PIE", 1, 1); 390 check_feature(ENABLE_FEAT_S2POE, read_feat_s2poe_id_field(), 391 "S2POE", 1, 1); 392 check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(), 393 "S1POE", 1, 1); 394 check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(), 395 "CSV2_3", 3, 3); 396 check_feature(ENABLE_FEAT_DEBUGV8P9, read_feat_debugv8p9_id_field(), 397 "DEBUGV8P9", 11, 11); 398 check_feature(ENABLE_FEAT_THE, read_feat_the_id_field(), 399 "THE", 1, 1); 400 check_feature(ENABLE_FEAT_SCTLR2, read_feat_sctlr2_id_field(), 401 "SCTLR2", 1, 1); 402 403 /* v9.0 features */ 404 check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(), 405 "BRBE", 1, 2); 406 check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(), 407 "TRBE", 1, 1); 408 409 /* v9.2 features */ 410 check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(), 411 "SME", 1, 2); 412 check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(), 413 "SME2", 2, 2); 414 check_feature(ENABLE_FEAT_FPMR, read_feat_fpmr_id_field(), 415 "FPMR", 1, 1); 416 417 /* v9.3 features */ 418 check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(), 419 "D128", 1, 1); 420 421 /* v9.4 features */ 422 check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1); 423 check_feature(ENABLE_RME, read_feat_rme_id_field(), "RME", 1, 1); 424 425 if (tainted) { 426 panic(); 427 } 428 } 429