build(qemu-sbsa): it is GICv3 platform

GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ibf9376caabbc05ceef4f870d8

build(qemu-sbsa): it is GICv3 platform

GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ibf9376caabbc05ceef4f870d816e6c60a344f895

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Merge "chore: remove MULTI_CONSOLE_API references" into integration

fix(qemu_sbsa): align FIP base to BL1 size

RME patch series shown that we can build larger BL1 than we can run:

NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.9(debug):v2.9.0-736-g08548888a
NOT

fix(qemu_sbsa): align FIP base to BL1 size

RME patch series shown that we can build larger BL1 than we can run:

NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.9(debug):v2.9.0-736-g08548888a
NOTICE: BL1: Built : 12:10:39, Sep 18 2023
INFO: BL1: RAM 0x3ffee000 - 0x3fffb000
INFO: BL1: Loading BL2
WARNING: Firmware Image Package header check failed.

RME pushed debug build BL1 over 0x8000 in size.
This exposed an error where FIP_BASE (supposed to be at BL1_SIZE offset
from start of flash) was actually 0x8000 and not 0x12000.
Make sure we have space for BL1 by deriving FIP_BASE from it.

Note: this is a breaking change for edk2 FD image generation, which had
similarly hardcoded a 0x8000 offset. These images must be updated in
lock-step.

Change-Id: I8a1a85e82319945a4412c424467d818d5b6e4ecd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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chore: remove MULTI_CONSOLE_API references

MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c99
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
reference

chore: remove MULTI_CONSOLE_API references

MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c99
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
references in platform.mk files and also in one rst which is not valid
anymore.

Change-Id: I45f8e7db0a14ce63de62509100d8159b7aca2657
Signed-off-by: Michal Simek <michal.simek@amd.com>

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refactor(qemu): move options to start of file

There are some variables to enable/disable options. Let keep them at top
of file.

Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: M

refactor(qemu): move options to start of file

There are some variables to enable/disable options. Let keep them at top
of file.

Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): handle SPM_MM builds

SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:

> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14

refactor(qemu): handle SPM_MM builds

SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:

> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14: *** "Error: SPM_MM is not compatible with ENABLE_SVE_FOR_NS". Stop.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Iabe181647fce00a432ae11dc4599b71619364c24

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refactor(qemu): handle AArch64 flags

Handle coherency in one place for AArch64 mode.

Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linar

refactor(qemu): handle AArch64 flags

Handle coherency in one place for AArch64 mode.

Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): common cpu features enablement

Enable SVE, SME, RNG, FGT in one place.

qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG

Signed-off-by: Marcin Juszkiewicz <ma

refactor(qemu): common cpu features enablement

Enable SVE, SME, RNG, FGT in one place.

qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I2e8f971ef3e42d9ebe9f20641b288cc8c40f806a

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refactor(qemu): common BL31 sources

Move BL31 source list into common file.

Change-Id: Iaa27cfd8f87b691728379c87a6ff6331e87951e1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

refactor(qemu): common BL1/2 sources

Move BL1 and BL2 source list into common file.

Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro

refactor(qemu): common BL1/2 sources

Move BL1 and BL2 source list into common file.

Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): move CPU definitions into one place

Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not

refactor(qemu): move CPU definitions into one place

Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not matter.

Change-Id: I5b8f7d18dc903e86e0cc7babbc2fb3f26a1bfdfa
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): move FDT stuff into one place

Move libfdt includes into common file and use definitions from them.

Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkie

refactor(qemu): move FDT stuff into one place

Move libfdt includes into common file and use definitions from them.

Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Change-Id: Id710e2b960e7938d2dbe7a88d9e158a7009fc3d1
Signed-off-by: Marcin Jus

feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Change-Id: Id710e2b960e7938d2dbe7a88d9e158a7009fc3d1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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feat(qemu_sbsa): handle GIC ITS address

Read data from DeviceTree provided by QEMU, provide via SMC
to the next firmware level.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Cha

feat(qemu_sbsa): handle GIC ITS address

Read data from DeviceTree provided by QEMU, provide via SMC
to the next firmware level.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I95c5f00ab2cca3b5fda122dcc8d7704a7a82059b

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feat(qemu-sbsa): handle GIC base

QEMU provides GIC information in DeviceTree (on platform version 0.1+).
Read it and provide to next firmware level via SMC.

Signed-off-by: Marcin Juszkiewicz <marci

feat(qemu-sbsa): handle GIC base

QEMU provides GIC information in DeviceTree (on platform version 0.1+).
Read it and provide to next firmware level via SMC.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I383919bd172acc8873292a0c5e4469651dc96fb9

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feat(qemu-sbsa): handle platform version

QEMU provides platform version information via DT. We want to use it
in firmware to handle differences between platform versions.

Signed-off-by: Marcin Jusz

feat(qemu-sbsa): handle platform version

QEMU provides platform version information via DT. We want to use it
in firmware to handle differences between platform versions.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I8def66dac9dd5d7ab0e459baa40e27a11b65f0ba

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fix(qemu-sbsa): enable FGT

QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.

So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.

Signed-off-by: Marcin Juszkiewicz <mar

fix(qemu-sbsa): enable FGT

QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.

So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I49fb3e742b69ce7be5666e0144525dde21a68238

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fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld

Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS ( for fixed/real platforms)
2:

fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld

Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS ( for fixed/real platforms)
2: FEAT_STATE_CHECK ( for configurable platforms)
to meet the feature detection requirements dynamically, mainly
targetting configurable/Fixed Virtual platforms.

With this mechanism in place, we are refactoring all the existing
feature flags to the FEAT_STATE_CHECK option(=2), including
FEAT_SVE explicitly for FVPs.

SVE Patch Reference:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19888/25

This newly introduced change, breaks the existing behaviour especially
for virtual platforms, who have set the ENABLE_SVE_FOR_NS flag to 1.

Moving ahead, we advise the platforms to take the following steps while
enabling the features:

1. If the platform is configurable (virtual), and want to ensure feature
detection happens dynamically at runtime, set the build flags to
FEAT_STATE_CHECK(=2).

2. For real(fixed) platforms, depending on the features supported by the
hardware and platform wants to enable it, platforms could set build
flags to FEAT_STATE_ALWAYS(=1).

(Note: Only the non-secure world enablement related build flags have
been refactored to take the values within 0 to 2. As earlier Secure
world enablement flags will still remain boolean.)

Henceforth, in order to keep it aligned with this tri-state mechanism,
changing the qemu platform default to the now supported dynamic
option(=2), so the right decision can be made by the code at runtime.

Change-Id: Icc95b8b872378b7874d4345b631adfc314e4dada
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(qemu): add "neoverse-n1" cpu support

Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c7111

feat(qemu): add "neoverse-n1" cpu support

Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c71115451ae91a1643812d89ec7c071f

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build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name

build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.

This change introduces the period prefix to all specialized section
names.

BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.

Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(qemu-sbsa): enable SVE and SME

Commit 337ff4f1dd6604738d79fd3fa275ae74d74256b2 enabled SVE/SME for
qemu platform. Let do the same for qemu-sbsa one too.

With this change I can boot Debian 'book

fix(qemu-sbsa): enable SVE and SME

Commit 337ff4f1dd6604738d79fd3fa275ae74d74256b2 enabled SVE/SME for
qemu platform. Let do the same for qemu-sbsa one too.

With this change I can boot Debian 'bookworm' installed using Max cpu.

Info from referenced commit:

Starting with QEMU v3.1.0 (Dec 2018), QEMU's TCG emulation engine supports
the SVE architecture extension. In QEMU v7.1.0 (Aug 2022) it also gained
SME support.

As it stands today, running TF-A under QEMU with "-cpu max" makes Linux
hang, because SME and SVE accesses trap to EL3, but are never handled
there. This is because the Linux kernel sees the SVE or SME feature bits,
and assumes firmware has enabled the feature for lower exception levels.
This requirement is described in the Linux kernel booting protocol.

Enable those features in the TF-A build, so that BL31 does the proper
EL3 setup to make the feature usable in non-secure world.
We check the actual feature bits before accessing SVE or SME registers,
so this is safe even for older QEMU version or when not running with
-cpu max. As SVE and SME are AArch64 features only, do not enable them
when building for AArch32.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I9ea1f91e6b801218d944e8a7d798d5ae568ed59a

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