1# 2# Copyright (c) 2022-2023, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# This file lists all of the architectural features, and initializes 8# and enables them based on the configured architecture version. 9 10# This file follows the following format: 11# - By default disable any mandatory features. 12# - Then Enable mandatory feature if applicable to an Arch Version. 13# - Disable or enable any optional feature this would be enabled/disabled if needed by platform. 14 15# 16################################################################################ 17# Set mandatory features by default to zero. 18################################################################################ 19# 20 21#---- 22# 8.1 23#---- 24 25# Flag to enable access to Privileged Access Never bit of PSTATE. 26ENABLE_FEAT_PAN := 0 27 28# Flag to enable Virtualization Host Extensions. 29ENABLE_FEAT_VHE := 0 30 31#---- 32# 8.2 33#---- 34 35# Enable RAS Support. 36ENABLE_FEAT_RAS := 0 37 38#---- 39# 8.3 40#---- 41 42# Flag to enable Pointer Authentication. Internal flag not meant for 43# direct setting. Use BRANCH_PROTECTION to enable PAUTH. 44ENABLE_PAUTH := 0 45 46# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 47# must be set to 1 if the platform wants to use this feature in the Secure 48# world. It is not necessary for use in the Non-secure world. 49CTX_INCLUDE_PAUTH_REGS := 0 50 51#---- 52# 8.4 53#---- 54 55# Flag to enable Secure EL-2 feature. 56ENABLE_FEAT_SEL2 := 0 57 58# Include nested virtualization control (Armv8.4-NV) registers in cpu context. 59# This must be set to 1 if architecture implements Nested Virtualization 60# Extension and platform wants to use this feature in the Secure world. 61CTX_INCLUDE_NEVE_REGS := 0 62 63# By default, disable trace filter control register access to lower non-secure 64# exception levels, i.e. NS-EL2, or NS-EL1 if NS-EL2 is implemented, but 65# trace filter control register access is unused if FEAT_TRF is implemented. 66ENABLE_TRF_FOR_NS := 0 67 68# Flag to enable Data Independent Timing instructions. 69ENABLE_FEAT_DIT := 0 70 71#---- 72# 8.5 73#---- 74 75# Flag to enable access to the Random Number Generator registers. 76ENABLE_FEAT_RNG := 0 77 78# Flag to enable Speculation Barrier Instruction. 79ENABLE_FEAT_SB := 0 80 81# Flag to enable Branch Target Identification. 82# Internal flag not meant for direct setting. 83# Use BRANCH_PROTECTION to enable BTI. 84ENABLE_BTI := 0 85 86#---- 87# 8.6 88#---- 89 90# Flag to enable access to the CNTPOFF_EL2 register. 91ENABLE_FEAT_ECV := 0 92 93# Flag to enable access to the HDFGRTR_EL2 register. 94ENABLE_FEAT_FGT := 0 95 96#---- 97# 8.7 98#---- 99 100# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn. 101ENABLE_FEAT_HCX := 0 102 103#---- 104# 8.9 105#---- 106 107# Flag to enable access to TCR2 (FEAT_TCR2). 108ENABLE_FEAT_TCR2 := 0 109 110# 111################################################################################ 112# Enable Mandatory features based on Arch versions. 113################################################################################ 114# 115 116# Enable the features which are mandatory from ARCH version 8.1 and upwards. 117ifeq "8.1" "$(word 1, $(sort 8.1 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" 118ENABLE_FEAT_PAN := 1 119ENABLE_FEAT_VHE := 1 120endif 121 122# Enable the features which are mandatory from ARCH version 8.2 and upwards. 123ifeq "8.2" "$(word 1, $(sort 8.2 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" 124ENABLE_FEAT_RAS := 1 125endif 126 127# Enable the features which are mandatory from ARCH version 8.4 and upwards. 128ifeq "8.4" "$(word 1, $(sort 8.4 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" 129ENABLE_FEAT_SEL2 := 1 130CTX_INCLUDE_NEVE_REGS := 1 131ENABLE_TRF_FOR_NS := 1 132ENABLE_FEAT_DIT := 1 133endif 134 135# Enable the features which are mandatory from ARCH version 8.5 and upwards. 136ifeq "8.5" "$(word 1, $(sort 8.5 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" 137ENABLE_FEAT_RNG := 1 138ENABLE_FEAT_SB := 1 139 140# Enable Memory tagging, Branch Target Identification for aarch64 only. 141ifeq ($(ARCH), aarch64) 142 mem_tag_arch_support := yes 143endif #(ARCH=aarch64) 144 145endif 146 147# Enable the features which are mandatory from ARCH version 8.6 and upwards. 148ifeq "8.6" "$(word 1, $(sort 8.6 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" 149ENABLE_FEAT_ECV := 1 150ENABLE_FEAT_FGT := 1 151endif 152 153# Enable the features which are mandatory from ARCH version 8.7 and upwards. 154ifeq "8.7" "$(word 1, $(sort 8.7 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" 155ENABLE_FEAT_HCX := 1 156endif 157 158# Enable the features which are mandatory from ARCH version 8.9 and upwards. 159ifeq "8.9" "$(word 1, $(sort 8.9 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" 160ENABLE_FEAT_TCR2 := 1 161endif 162 163# 164################################################################################ 165# Optional Features defaulted to 0 or 2, if they are not enabled from 166# build option. Can also be disabled or enabled by platform if needed. 167################################################################################ 168# 169 170#---- 171# 8.0 172#---- 173 174# Flag to enable CSV2_2 extension. 175ENABLE_FEAT_CSV2_2 ?= 0 176 177# By default, disable access of trace system registers from NS lower 178# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if 179# system register trace is implemented. This feature is available if 180# trace unit such as ETMv4.x, This feature is OPTIONAL and is only 181# permitted in Armv8 implementations. 182ENABLE_SYS_REG_TRACE_FOR_NS ?= 0 183 184#---- 185# 8.2 186#---- 187 188# Build option to enable/disable the Statistical Profiling Extension, 189# keep it enabled by default for AArch64. 190ifeq (${ARCH},aarch64) 191 ENABLE_SPE_FOR_NS ?= 2 192else ifeq (${ARCH},aarch32) 193 ifdef ENABLE_SPE_FOR_NS 194 $(error ENABLE_SPE_FOR_NS is not supported for AArch32) 195 else 196 ENABLE_SPE_FOR_NS := 0 197 endif 198endif 199 200# Enable SVE for non-secure world by default. 201ifeq (${ARCH},aarch64) 202 ENABLE_SVE_FOR_NS ?= 2 203# SVE is only supported on AArch64 so disable it on AArch32. 204else ifeq (${ARCH},aarch32) 205 ifdef ENABLE_SVE_FOR_NS 206 $(error ENABLE_SVE_FOR_NS is not supported for AArch32) 207 else 208 ENABLE_SVE_FOR_NS := 0 209 endif 210endif 211 212#---- 213# 8.4 214#---- 215 216# Feature flags for supporting Activity monitor extensions. 217ENABLE_FEAT_AMU ?= 0 218ENABLE_AMU_AUXILIARY_COUNTERS ?= 0 219ENABLE_AMU_FCONF ?= 0 220AMU_RESTRICT_COUNTERS ?= 0 221 222# Build option to enable MPAM for lower ELs. 223ENABLE_MPAM_FOR_LOWER_ELS ?= 0 224 225#---- 226# 8.5 227#---- 228 229# Flag to enable support for EL3 trapping of reads of the RNDR and RNDRRS 230# registers, by setting SCR_EL3.TRNDR. 231ENABLE_FEAT_RNG_TRAP ?= 0 232 233# Include Memory Tagging Extension registers in cpu context. This must be set 234# to 1 if the platform wants to use this feature in the Secure world and MTE is 235# enabled at ELX. 236CTX_INCLUDE_MTE_REGS ?= 0 237 238#---- 239# 8.6 240#---- 241 242# Flag to enable AMUv1p1 extension. 243ENABLE_FEAT_AMUv1p1 ?= 0 244 245# Flag to enable delayed trapping of WFE instruction (FEAT_TWED). 246ENABLE_FEAT_TWED ?= 0 247 248# In v8.6+ platforms with delayed trapping of WFE being supported 249# via FEAT_TWED, this flag takes the delay value to be set in the 250# SCR_EL3.TWEDEL(4bit) field, when FEAT_TWED is implemented. 251# By default it takes 0, and need to be updated by the platforms. 252TWED_DELAY ?= 0 253 254# Disable MTPMU if FEAT_MTPMU is supported. 255DISABLE_MTPMU ?= 0 256 257#---- 258# 8.9 259#---- 260 261# Flag to enable NoTagAccess memory region attribute for stage 2 of translation. 262ENABLE_FEAT_MTE_PERM ?= 0 263 264# Flag to enable access to Stage 2 Permission Indirection (FEAT_S2PIE). 265ENABLE_FEAT_S2PIE ?= 0 266 267# Flag to enable access to Stage 1 Permission Indirection (FEAT_S1PIE). 268ENABLE_FEAT_S1PIE ?= 0 269 270# Flag to enable access to Stage 2 Permission Overlay (FEAT_S2POE). 271ENABLE_FEAT_S2POE ?= 0 272 273# Flag to enable access to Stage 1 Permission Overlay (FEAT_S1POE). 274ENABLE_FEAT_S1POE ?= 0 275 276#---- 277# 9.0 278#---- 279 280# Flag to enable Realm Management Extension (FEAT_RME). 281ENABLE_RME ?= 0 282 283# Scalable Matrix Extension for non-secure world. 284ENABLE_SME_FOR_NS ?= 0 285 286# Scalable Vector Extension for secure world. 287ENABLE_SVE_FOR_SWD ?= 0 288 289# By default, disable access of trace buffer control registers from NS 290# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 291# if FEAT_TRBE is implemented. 292# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in 293# AArch32. 294ifeq (${ARCH},aarch64) 295 ENABLE_TRBE_FOR_NS ?= 0 296else ifeq (${ARCH},aarch32) 297 ifdef ENABLE_TRBE_FOR_NS 298 $(error ENABLE_TRBE_FOR_NS is not supported for AArch32) 299 else 300 ENABLE_TRBE_FOR_NS := 0 301 endif 302endif 303 304#---- 305# 9.2 306#---- 307 308# Scalable Matrix Extension version 2 for non-secure world. 309ENABLE_SME2_FOR_NS ?= 0 310 311# Scalable Matrix Extension for secure world. 312ENABLE_SME_FOR_SWD ?= 0 313 314# By default, disable access to branch record buffer control registers from NS 315# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 316# if FEAT_BRBE is implemented. 317ENABLE_BRBE_FOR_NS ?= 0 318 319#---- 320#9.4 321#---- 322 323# Flag to enable access to Guarded Control Stack (FEAT_GCS). 324ENABLE_FEAT_GCS ?= 0 325