| b67a7c7c | 09-Jan-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: support for the latest platform port handlers
This patch adds support for the newer platform handler functions. Commit
I6db74b020b141048b6b8c03e1bef7ed8f72fd75b merges the upstream code wh
Tegra186: support for the latest platform port handlers
This patch adds support for the newer platform handler functions. Commit
I6db74b020b141048b6b8c03e1bef7ed8f72fd75b merges the upstream code which
has already moved all the upstream supported platforms over to these
handler functions.
Change-Id: I621eff038f3c0dc1b90793edcd4dd7c71b196045
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| b6ea86b1 | 07-Jan-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: implement prepare_system_reset handler
This patch implements the 'prepare_system_reset' handler to
issue the 'system reset' command to the MCE.
Change-Id: I83d8d0b4167aac5963d640fe77d5754
Tegra186: implement prepare_system_reset handler
This patch implements the 'prepare_system_reset' handler to
issue the 'system reset' command to the MCE.
Change-Id: I83d8d0b4167aac5963d640fe77d5754dc7ef05b1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 348619f2 | 05-Jan-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: implement CPU_OFF handler
This patch implements the CPU_OFF handler for powering down
a CPU using the MCE driver.
Change-Id: I8d455005d0b547cc61cc7778bfe9eb84b7e5480c
Signed-off-by: Varun
Tegra186: implement CPU_OFF handler
This patch implements the CPU_OFF handler for powering down
a CPU using the MCE driver.
Change-Id: I8d455005d0b547cc61cc7778bfe9eb84b7e5480c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 5d74d68e | 04-Jan-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: update SYSCNT_FREQ to 31.25MHz
The System Counter Frequency has been updated to 31.25MHz after
some experiments as the previous value was too high.
Change-Id: I79986ee1c0c88700a3a2b1dbff2
Tegra186: update SYSCNT_FREQ to 31.25MHz
The System Counter Frequency has been updated to 31.25MHz after
some experiments as the previous value was too high.
Change-Id: I79986ee1c0c88700a3a2b1dbff2d3f00c0c412b9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| b5ef9569 | 30-Nov-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: relocate bl31.bin to the SYSRAM
Tegra186 has an on-die, 320KB, "System RAM" memory. Out of the total
size, 256KB are allocated for the CPU TrustZone binaries - EL3 monitor
and Trusted OS.
Tegra186: relocate bl31.bin to the SYSRAM
Tegra186 has an on-die, 320KB, "System RAM" memory. Out of the total
size, 256KB are allocated for the CPU TrustZone binaries - EL3 monitor
and Trusted OS.
This patch changes the base address for bl31.bin to the SysRAM base
address. The carveout is too small for the Trusted OS, so we relocate
only the monitor binary.
Change-Id: Ib4b667ff2a7a619589851338f9d0bfb02078c575
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| c7ec0892 | 14-Mar-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: implement prepare_system_off handler
This patch issues the 'System Off' ARI to power off the entire
system from the 'prepare_system_off' handler.
Signed-off-by: Varun Wadekar <vwadekar@nv
Tegra186: implement prepare_system_off handler
This patch issues the 'System Off' ARI to power off the entire
system from the 'prepare_system_off' handler.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| b47d97b3 | 14-Sep-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: power on/off secondary CPUs
This patch add code to power on/off the secondary CPUs on the Tegra186
chip. The MCE block is the actual hardware that takes care of the
power on/off sequence.
Tegra186: power on/off secondary CPUs
This patch add code to power on/off the secondary CPUs on the Tegra186
chip. The MCE block is the actual hardware that takes care of the
power on/off sequence. We pass the constructed CPU #, depending on the
MIDR_IMPL field, to the MCE CPU handlers.
This patch also programs the reset vector addresses to allow the
CPUs to power on through the monitor and then jump to the linux
world.
Change-Id: Idc164586cda91c2009d66f3e09bf4464de9662db
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| bb844c1f | 09-Sep-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: SiP calls to interact with the MCE driver
This patch adds the new SiP SMC calls to allow the NS world to
interact with the MCE hardware block on Tegra186 chips.
Change-Id: I79c6b9f76d68a8
Tegra186: SiP calls to interact with the MCE driver
This patch adds the new SiP SMC calls to allow the NS world to
interact with the MCE hardware block on Tegra186 chips.
Change-Id: I79c6b9f76d68a87abd57a940613ec070562d2eac
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 7808b06b | 14-Mar-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: mce: driver for the CPU complex power manager block
The CPU Complex (CCPLEX) Power Manager (Denver MCE, or DMCE) is an
offload engine for BPMP to do voltage related sequencing and for
hard
Tegra186: mce: driver for the CPU complex power manager block
The CPU Complex (CCPLEX) Power Manager (Denver MCE, or DMCE) is an
offload engine for BPMP to do voltage related sequencing and for
hardware requests to be handled in a better latency than BPMP-firmware.
There are two interfaces to the MCEs - Abstract Request Interface (ARI)
and the traditional NVGINDEX/NVGDATA interface.
MCE supports various commands which can be used by CPUs - ARM as well
as Denver, for power management and reset functionality. Since the
linux kernel is the master for all these scenarios, each MCE command
can be issued by a corresponding SMC. These SMCs have been moved to
SiP SMC space as they are specific to the Tegra186 SoC.
Change-Id: I67bee83d2289a8ab63bc5556e5744e5043803e51
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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