1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <debug.h> 38 #include <mce.h> 39 #include <psci.h> 40 #include <t18x_ari.h> 41 #include <tegra_private.h> 42 43 int32_t tegra_soc_validate_power_state(unsigned int power_state) 44 { 45 /* Sanity check the requested afflvl */ 46 if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { 47 /* 48 * It's possible to enter standby only on affinity level 0 i.e. 49 * a cpu on Tegra. Ignore any other affinity level. 50 */ 51 if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0) 52 return PSCI_E_INVALID_PARAMS; 53 } 54 55 return PSCI_E_SUCCESS; 56 } 57 58 int tegra_soc_prepare_cpu_on(unsigned long mpidr) 59 { 60 int target_cpu = mpidr & MPIDR_CPU_MASK; 61 int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 62 MPIDR_AFFINITY_BITS; 63 64 if (target_cluster > MPIDR_AFFLVL1) { 65 ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); 66 return PSCI_E_NOT_PRESENT; 67 } 68 69 /* construct the target CPU # */ 70 target_cpu |= (target_cluster << 2); 71 72 mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); 73 74 return PSCI_E_SUCCESS; 75 } 76 77 int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr) 78 { 79 /* 80 * Check if we are exiting from SOC_POWERDN. 81 */ 82 if (tegra_system_suspended()) { 83 84 /* 85 * System resume complete. 86 */ 87 tegra_pm_system_suspend_exit(); 88 } 89 90 return PSCI_E_SUCCESS; 91 } 92 93 int tegra_soc_prepare_cpu_off(unsigned long mpidr) 94 { 95 cpu_context_t *ctx = cm_get_context(NON_SECURE); 96 gp_regs_t *gp_regs = get_gpregs_ctx(ctx); 97 98 assert(ctx); 99 assert(gp_regs); 100 101 /* Turn off wake_mask */ 102 write_ctx_reg(gp_regs, CTX_GPREG_X4, 0); 103 write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); 104 write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); 105 mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC7, 106 0, TEGRA_ARI_SYSTEM_SC7); 107 108 /* Turn off CPU */ 109 return mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, 110 ~0, 0); 111 } 112 113 __dead2 void tegra_soc_prepare_system_off(void) 114 { 115 mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF); 116 } 117