1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <debug.h> 38 #include <mce.h> 39 #include <psci.h> 40 #include <t18x_ari.h> 41 #include <tegra_private.h> 42 43 int32_t tegra_soc_validate_power_state(unsigned int power_state, 44 psci_power_state_t *req_state) 45 { 46 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 47 48 /* Sanity check the requested afflvl */ 49 if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { 50 /* 51 * It's possible to enter standby only on affinity level 0 i.e. 52 * a cpu on Tegra. Ignore any other affinity level. 53 */ 54 if (pwr_lvl != MPIDR_AFFLVL0) 55 return PSCI_E_INVALID_PARAMS; 56 57 /* power domain in standby state */ 58 req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE; 59 } 60 61 return PSCI_E_SUCCESS; 62 } 63 64 int tegra_soc_pwr_domain_on(u_register_t mpidr) 65 { 66 int target_cpu = mpidr & MPIDR_CPU_MASK; 67 int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 68 MPIDR_AFFINITY_BITS; 69 70 if (target_cluster > MPIDR_AFFLVL1) { 71 ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); 72 return PSCI_E_NOT_PRESENT; 73 } 74 75 /* construct the target CPU # */ 76 target_cpu |= (target_cluster << 2); 77 78 mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); 79 80 return PSCI_E_SUCCESS; 81 } 82 83 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 84 { 85 cpu_context_t *ctx = cm_get_context(NON_SECURE); 86 gp_regs_t *gp_regs = get_gpregs_ctx(ctx); 87 88 assert(ctx); 89 assert(gp_regs); 90 91 /* Turn off wake_mask */ 92 write_ctx_reg(gp_regs, CTX_GPREG_X4, 0); 93 write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); 94 write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); 95 mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC7, 96 0, TEGRA_ARI_SYSTEM_SC7); 97 98 /* Turn off CPU */ 99 return mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, 100 ~0, 0); 101 } 102 103 __dead2 void tegra_soc_prepare_system_off(void) 104 { 105 mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF); 106 } 107 108 int tegra_soc_prepare_system_reset(void) 109 { 110 mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT); 111 112 return PSCI_E_SUCCESS; 113 } 114