1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <debug.h> 34 #include <mce.h> 35 #include <psci.h> 36 #include <t18x_ari.h> 37 #include <tegra_private.h> 38 39 int32_t tegra_soc_validate_power_state(unsigned int power_state) 40 { 41 /* Sanity check the requested afflvl */ 42 if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { 43 /* 44 * It's possible to enter standby only on affinity level 0 i.e. 45 * a cpu on Tegra. Ignore any other affinity level. 46 */ 47 if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0) 48 return PSCI_E_INVALID_PARAMS; 49 } 50 51 return PSCI_E_SUCCESS; 52 } 53 54 int tegra_soc_prepare_cpu_on(unsigned long mpidr) 55 { 56 int target_cpu = mpidr & MPIDR_CPU_MASK; 57 int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 58 MPIDR_AFFINITY_BITS; 59 60 if (target_cluster > MPIDR_AFFLVL1) { 61 ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); 62 return PSCI_E_NOT_PRESENT; 63 } 64 65 /* construct the target CPU # */ 66 target_cpu |= (target_cluster << 2); 67 68 mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); 69 70 return PSCI_E_SUCCESS; 71 } 72 73 int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr) 74 { 75 /* 76 * Check if we are exiting from SOC_POWERDN. 77 */ 78 if (tegra_system_suspended()) { 79 80 /* 81 * System resume complete. 82 */ 83 tegra_pm_system_suspend_exit(); 84 } 85 86 return PSCI_E_SUCCESS; 87 } 88 89 int tegra_soc_prepare_cpu_off(unsigned long mpidr) 90 { 91 /* Turn off wake_mask */ 92 mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, 0, 0, 1); 93 94 /* Turn off CPU */ 95 return mce_command_handler(MCE_CMD_ENTER_CSTATE, ~0, 0, 0); 96 } 97 98 __dead2 void tegra_soc_prepare_system_off(void) 99 { 100 mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF); 101 } 102