1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <debug.h> 34 #include <mce.h> 35 #include <psci.h> 36 #include <tegra_private.h> 37 38 int32_t tegra_soc_validate_power_state(unsigned int power_state) 39 { 40 /* Sanity check the requested afflvl */ 41 if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { 42 /* 43 * It's possible to enter standby only on affinity level 0 i.e. 44 * a cpu on Tegra. Ignore any other affinity level. 45 */ 46 if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0) 47 return PSCI_E_INVALID_PARAMS; 48 } 49 50 return PSCI_E_SUCCESS; 51 } 52 53 int tegra_soc_prepare_cpu_on(unsigned long mpidr) 54 { 55 int target_cpu = mpidr & MPIDR_CPU_MASK; 56 int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 57 MPIDR_AFFINITY_BITS; 58 59 if (target_cluster > MPIDR_AFFLVL1) { 60 ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); 61 return PSCI_E_NOT_PRESENT; 62 } 63 64 /* construct the target CPU # */ 65 target_cpu |= (target_cluster << 2); 66 67 mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); 68 69 return PSCI_E_SUCCESS; 70 } 71 72 int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr) 73 { 74 /* 75 * Check if we are exiting from SOC_POWERDN. 76 */ 77 if (tegra_system_suspended()) { 78 79 /* 80 * System resume complete. 81 */ 82 tegra_pm_system_suspend_exit(); 83 } 84 85 return PSCI_E_SUCCESS; 86 } 87 88 int tegra_soc_prepare_cpu_off(unsigned long mpidr) 89 { 90 /* Turn off wake_mask */ 91 mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, 0, 0, 1); 92 93 /* Turn off CPU */ 94 return mce_command_handler(MCE_CMD_ENTER_CSTATE, ~0, 0, 0); 95 } 96