Tegra: prepare boot parameters for Trusty

This patch saves the boot parameters provided by the previous bootloader
during cold boot and passes them to Trusty. Commit 06ff251ec introduced
the plat_tr

Tegra: prepare boot parameters for Trusty

This patch saves the boot parameters provided by the previous bootloader
during cold boot and passes them to Trusty. Commit 06ff251ec introduced
the plat_trusty_set_boot_args() handler, but did not consider the boot
parameters passed by the previous bootloader. This patch fixes that
anomaly.

Change-Id: Ib40dcd02b67c94cea5cefce09edb0be4a998db37
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: per-CPU GIC CPU interface init

This patch enables per-CPU GIC CPU interfaces during CPU
power on. The previous code initialized the distributor
for all CPUs, which was not required.

Signed-o

Tegra: per-CPU GIC CPU interface init

This patch enables per-CPU GIC CPU interfaces during CPU
power on. The previous code initialized the distributor
for all CPUs, which was not required.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifd957b2367da06405b4c3e2225411adbaec35bb8

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Tegra: introduce plat_enable_console()

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while a

Tegra: introduce plat_enable_console()

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.

For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.

Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Revert "Tegra: Add support for fake system suspend"

This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e

Fake system suspend relies on software running on EL3
to trigger a warm reset.

Reve

Revert "Tegra: Add support for fake system suspend"

This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e

Fake system suspend relies on software running on EL3
to trigger a warm reset.

Revert enabling fake system suspend, as the software
running on El3 is not allowed to trigger a warm reset.

Change-Id: I6035f2a7bcb0a4ad50a62c5bc5239226c625ee5e
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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Tegra: memctrl_v2: fix "overflow before widen" coverity issue

This patch fixes a coding error, where the size of the protected memory area
was truncated due to an incorrect typecast.

This defect wa

Tegra: memctrl_v2: fix "overflow before widen" coverity issue

This patch fixes a coding error, where the size of the protected memory area
was truncated due to an incorrect typecast.

This defect was found by coverity and reported as CID 336781.

Change-Id: I41878b0a9a5e5cd78ef3393fdc7b9ea7f7403ed3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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tegra: add support for multi console interface

This patch updates all Tegra platforms to use the new multi console API.

Change-Id: I27c0c7830a86e26491dea9991a689f0b01e4dbf0
Signed-off-by: Ambroise

tegra: add support for multi console interface

This patch updates all Tegra platforms to use the new multi console API.

Change-Id: I27c0c7830a86e26491dea9991a689f0b01e4dbf0
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Julius Werner <jwerner@chromium.org>

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Tegra: Fix typo in comment

initilise -> initialise

Signed-off-by: Andreas Färber <afaerber@suse.de>
Change-Id: Ib129e6bd48623b6565b669bc674208893a2f7668

Tegra: Extend NS address check error output

Let bl31_check_ns_address() print the address it doesn't like.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Change-Id: I29a4fb33c24e9f7464ccd2ea44a46

Tegra: Extend NS address check error output

Let bl31_check_ns_address() print the address it doesn't like.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Change-Id: I29a4fb33c24e9f7464ccd2ea44a4608f5cfe5be6

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Makefile: remove extra include paths in INCLUDES

Now it is needed to use the full path of the common header files.

Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more
informatio

Makefile: remove extra include paths in INCLUDES

Now it is needed to use the full path of the common header files.

Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more
information.

Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Tegra: dummy support for the io_storage backend

This patch provides dummy macros and platform files to compile
the io_storage driver backend. This patch is necessary to
remove the "--unresolved=el3_

Tegra: dummy support for the io_storage backend

This patch provides dummy macros and platform files to compile
the io_storage driver backend. This patch is necessary to
remove the "--unresolved=el3_panic" linker flag from Tegra's
makefiles and allow us to revert this workaround, previously
suggested by the ARM toolchain team.

The "--unresolved=el3_panic" flag actually was a big hammer that
allowed Tegra platforms to work with armlink previously but it
masks legit errors with the code as well.

Change-Id: I0421d35657823215229f84231896b84167f90548
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: initialise per-CPU GIC interface(s)

This patch initilises the per-CPU GIC bits during cold boot and
secondary CPU power up. Commit 80c50ee accidentally left out this
part.

Change-Id: I73ce59

Tegra: initialise per-CPU GIC interface(s)

This patch initilises the per-CPU GIC bits during cold boot and
secondary CPU power up. Commit 80c50ee accidentally left out this
part.

Change-Id: I73ce59dbc83580a84b827cab89fe7e1f65f9f130
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: spe: prepend '\r' to '\n'

This patch udpates the SPE console driver to prepend '\r' to
'\n'. This fixes the alignment of prints seen by the host
machines on their UART ports.

Tested by colle

Tegra: spe: prepend '\r' to '\n'

This patch udpates the SPE console driver to prepend '\r' to
'\n'. This fixes the alignment of prints seen by the host
machines on their UART ports.

Tested by collecting the logs from host PC using Cutecom

Reported by: Mustafa Bilgen <mbilgen@nvidia.com>

Change-Id: I6e0b412bd71ff5eb889582071df8c157da5175ed
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: Enable irq as wake-up event for cpu_standby

As per ARM ARM D1.17.2, any physical IRQ interrupt received by the PE
will be treated as a wake-up event, if SCR_EL3.IRQ is set to '1',
irrespectiv

Tegra: Enable irq as wake-up event for cpu_standby

As per ARM ARM D1.17.2, any physical IRQ interrupt received by the PE
will be treated as a wake-up event, if SCR_EL3.IRQ is set to '1',
irrespective of the value of the PSTATE.I bit value.

This patch programs the SCR_EL3.IRQ bit before entering CPU standby
state, to allow an IRQ to wake the PE. On waking up, the previous
SCR_EL3 value is restored.

Change-Id: Ie81cf3a7668f5ac35f4bf2ecc461b91b9b60650c
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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Tegra: bpmp: mark device "not present" on boot timeout

This patch updates the state machine to "not present" if the bpmp
firmware is not found in the system during boot. The suspend
handler also che

Tegra: bpmp: mark device "not present" on boot timeout

This patch updates the state machine to "not present" if the bpmp
firmware is not found in the system during boot. The suspend
handler also checks now if the interface exists, before updating
the internal state machine.

Reported by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

Change-Id: If8fd7f8e412bb603944555c24826855226e7f48c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: clear PMC_DPD registers on resume

This patch clears the PMC's DPD registers on resuming from System
Suspend, for all Tegra210 platforms that support the sc7entry-fw.

Change-Id: I7881ef0a5

Tegra210: clear PMC_DPD registers on resume

This patch clears the PMC's DPD registers on resuming from System
Suspend, for all Tegra210 platforms that support the sc7entry-fw.

Change-Id: I7881ef0a5f609ed28b158bc2f4016abea3c7f305
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>

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Tegra: bpmp: suspend/resume handlers

This patch adds suspend and resume handlers for the BPMP
interface. Mark the interface as "suspended" before entering
System Suspend and verify that BPMP is aliv

Tegra: bpmp: suspend/resume handlers

This patch adds suspend and resume handlers for the BPMP
interface. Mark the interface as "suspended" before entering
System Suspend and verify that BPMP is alive on exit.

Change-Id: I74ccbc86125079b46d06360fc4c7e8a5acfbdfb2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: support for System Suspend using sc7entry-fw binary

This patch adds support to enter System Suspend on Tegra210 platforms
without the traditional BPMP firmware. The BPMP firmware will no long

Tegra: support for System Suspend using sc7entry-fw binary

This patch adds support to enter System Suspend on Tegra210 platforms
without the traditional BPMP firmware. The BPMP firmware will no longer
be supported on Tegra210 platforms and its functionality will be
divided across the CPU and sc7entry-fw.

The sc7entry-fw takes care of performing the hardware sequence required
to enter System Suspend (SC7 power state) from the COP. The CPU is required
to load this firmware to the internal RAM of the COP and start the sequence.
The CPU also make sure that the COP is off after cold boot and is only
powered on when we want to start the actual System Suspend sequence.

The previous bootloader loads the firmware to TZDRAM and passes its base and
size as part of the boot parameters. The EL3 layer is supposed to sanitize
the parameters before touching the firmware blob.

To assist the warmboot code with the PMIC discovery, EL3 is also supposed to
program PMC's scratch register #210, with appropriate values. Without these
settings the warmboot code wont be able to get the device out of System
Suspend.

Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: pmc: helper function to find last ON CPU

This patch adds a helper function to find the last standing CPU
in a cluster.

Change-Id: Id018f1958f458c772c7b0c52af8ddf7532b1cec5
Signed-off-by: Var

Tegra: pmc: helper function to find last ON CPU

This patch adds a helper function to find the last standing CPU
in a cluster.

Change-Id: Id018f1958f458c772c7b0c52af8ddf7532b1cec5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: organize memory/mmio apertures to decrease memmap latency

This patch organizes the memory and mmio maps linearly, to make the
mmap_add_region process faster. The microsecond timer has been mo

Tegra: organize memory/mmio apertures to decrease memmap latency

This patch organizes the memory and mmio maps linearly, to make the
mmap_add_region process faster. The microsecond timer has been moved
to individual platforms instead of making it a common step, as it
further speeds up the memory map creation process.

Change-Id: I6fdaee392f7ac5d99daa182380ca9116a001f5d6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: flowctrl: helper functions to assist with cluster power states

This patch adds helper functions to help platforms with cluster state entry
and exit decisions.

* tegra_fc_ccplex_pgexit_lock()

Tegra: flowctrl: helper functions to assist with cluster power states

This patch adds helper functions to help platforms with cluster state entry
and exit decisions.

* tegra_fc_ccplex_pgexit_lock(): lock CPU power ungate
* tegra_fc_ccplex_pgexit_unlock(): unlock CPU power ungate
* tegra_fc_is_ccx_allowed(): CCx state entry allowed on this CPU?

Change-Id: I6490d34bf380dc03ae203eb3028f61984f06931c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: bpmp: remove bpmp init failed error print

This patch removes the error print displayed when bpmp init
fails. On platforms that do not load the bpmp firmware, this
print is seen on every clust

Tegra: bpmp: remove bpmp init failed error print

This patch removes the error print displayed when bpmp init
fails. On platforms that do not load the bpmp firmware, this
print is seen on every cluster idle and powerdown request,
cluttering the logs.

Change-Id: I9e30007a913080406052fc32d5360ff70a019d75
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: fiq_glue: support to handle LEGACY_FIQ PPIs for Tegra SoCs

This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT

Tegra: fiq_glue: support to handle LEGACY_FIQ PPIs for Tegra SoCs

This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT_LEGACY_FIQ_HANDLING
configuration variable and is only enabled for Tegra210 platforms, for now.

Change-Id: I0752ef54a986c58305e1bc8ad9be71d4a8bbd394
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing

On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the fl

Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing

On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the flow controller instead, for
power state management. But the flow controller can route the FIQ to the GICD,
as a PPI, which can then get routed to the target CPU.

This patch adds routines to enable/disable routing the legacy FIQ used by
the watchdog timers, to the GICD.

Change-Id: Idd07c88c8d730b5f0e93e3a6e4fdc59bdcb2161b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: SiP: set GPU in reset after vpr resize

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There

Tegra: SiP: set GPU in reset after vpr resize

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There exists a scenario, where the GPU might be out before we
program the new VPR parameters. This means, the GPU would still be
using older settings and leak secrets.

This patch puts the GPU back into reset, if it is out of reset after
resizing VPR, to mitigate this hole.

Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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Tegra: handle FIQ interrupts when NS handler is not registered

This patch updates the secure interrupt handler to mark the interrupt
as complete in case the NS world has not registered a handler.

C

Tegra: handle FIQ interrupts when NS handler is not registered

This patch updates the secure interrupt handler to mark the interrupt
as complete in case the NS world has not registered a handler.

Change-Id: Iebe952305f7db46375303699b6150611439475df
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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