| b42192bc | 21-Aug-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra210: wait for 512 timer ticks before retention entry
This patch programs the CPUECTLR_EL1 and L2ECTLR_EL1 registers,
so that the core waits for 512 generic timer CNTVALUEB ticks before
entering
Tegra210: wait for 512 timer ticks before retention entry
This patch programs the CPUECTLR_EL1 and L2ECTLR_EL1 registers,
so that the core waits for 512 generic timer CNTVALUEB ticks before
entering retention state, after executing a WFI instruction.
This functionality is configurable and can be enabled for platforms
by setting the newly defined 'ENABLE_L2_DYNAMIC_RETENTION' and
'ENABLE_CPU_DYNAMIC_RETENTION' flag.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| b25f5801 | 11-Aug-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memmap the actual memory available for BL31
On Tegra SoCs, the TZDRAM contains the BL31 and BL32 images. This patch
uses only the actual memory available for BL31 instead of mapping the
entir
Tegra: memmap the actual memory available for BL31
On Tegra SoCs, the TZDRAM contains the BL31 and BL32 images. This patch
uses only the actual memory available for BL31 instead of mapping the
entire TZDRAM.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 0bf1b022 | 31-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: retrieve BL32's bootargs from bl32_ep_info
This patch removes the bootargs pointer from the platform params
structure. Instead the bootargs are passed by the BL2 in the
bl32_ep_info struct wh
Tegra: retrieve BL32's bootargs from bl32_ep_info
This patch removes the bootargs pointer from the platform params
structure. Instead the bootargs are passed by the BL2 in the
bl32_ep_info struct which is a part of the EL3 params struct.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| e7d4caa2 | 16-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: Support for Tegra's T132 platforms
This patch implements support for T132 (Denver CPU) based Tegra
platforms.
The following features have been added:
* SiP calls to switch T132 CPU's AARCH
Tegra: Support for Tegra's T132 platforms
This patch implements support for T132 (Denver CPU) based Tegra
platforms.
The following features have been added:
* SiP calls to switch T132 CPU's AARCH mode
* Complete PSCI support, including 'System Suspend'
* Platform specific MMIO settings
* Locking of CPU vector registers
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 93eafbca | 23-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: implement per-SoC validate_power_state() handler
The validate_power_state() handler checks the power_state for a valid afflvl
and state id. Although the afflvl check is common, the state ids
Tegra: implement per-SoC validate_power_state() handler
The validate_power_state() handler checks the power_state for a valid afflvl
and state id. Although the afflvl check is common, the state ids are implementation
defined.
This patch moves the handler to the tegra/soc folder to allow each SoC to validate
the power_state for supported parameters.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| fb11a62f | 21-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: T210: include CPU files from SoC's platform.mk
This patch moves the inclusion of CPU code (A53, A57) to T210's
makefile. This way we can reduce code size for Tegra platforms by
including only
Tegra: T210: include CPU files from SoC's platform.mk
This patch moves the inclusion of CPU code (A53, A57) to T210's
makefile. This way we can reduce code size for Tegra platforms by
including only the required CPU files.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 8061a973 | 16-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs
A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to
enable read/write access to the L2 and CPUECTRL registers.
Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs
A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to
enable read/write access to the L2 and CPUECTRL registers. T210 is the
only platform that needs to enable this config for now.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 764c57f6 | 16-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: PMC: lock SCRATCH22 register
The PMC Scratch22 register contains the CPU reset vector to
be used by the warmboot code to power up the CPU while resuming
from system suspend. This patch locks
Tegra: PMC: lock SCRATCH22 register
The PMC Scratch22 register contains the CPU reset vector to
be used by the warmboot code to power up the CPU while resuming
from system suspend. This patch locks this PMC register to avoid
any further writes.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 2e7aea3d | 16-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: PMC: check if a CPU is already online
This patch checks if the target CPU is already online before
proceeding with it's power ON sequence.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> |
| 6a367fd1 | 08-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: Fix the delay loop used during SC7 exit
This patch fixes the delay loop used to wake up the BPMP during SC7 exit.
The earlier loop would fail just when the timer was about to wrap-around
(e.g
Tegra: Fix the delay loop used during SC7 exit
This patch fixes the delay loop used to wake up the BPMP during SC7 exit.
The earlier loop would fail just when the timer was about to wrap-around
(e.g. when TEGRA_TMRUS_BASE is 0xfffffffe, the target value becomes 0,
which would cause the loop to exit before it's expiry).
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| c8961326 | 16-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: introduce delay timer support
This patch introduces the backend required for implementing the delay
timer API. Tegra has an on-chip free flowing us timer which can be
used as the delay timer.
Tegra: introduce delay timer support
This patch introduces the backend required for implementing the delay
timer API. Tegra has an on-chip free flowing us timer which can be
used as the delay timer.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 68e2a641 | 08-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: Exclude coherent memory region from memory map
This patch sets the 'USE_COHERENT_MEM' flag to '0', so that the
coherent memory region will not be included in the memory map.
Signed-off-by: V
Tegra: Exclude coherent memory region from memory map
This patch sets the 'USE_COHERENT_MEM' flag to '0', so that the
coherent memory region will not be included in the memory map.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 94c672e7 | 03-Jul-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Implement get_sys_suspend_power_state() handler for Tegra
This patch implements the get_sys_suspend_power_state() handler required by
the PSCI SYSTEM_SUSPEND API. The intent of this handler is to re
Implement get_sys_suspend_power_state() handler for Tegra
This patch implements the get_sys_suspend_power_state() handler required by
the PSCI SYSTEM_SUSPEND API. The intent of this handler is to return the
appropriate State-ID field which can be utilized in `affinst_suspend()` to
suspend to system affinity level.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| e1e094c7 | 16-Jun-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Add missing features to the Tegra GIC driver
In order to handle secure/non-secure interrupts, overload the plat_ic_*
functions and copy GIC helper functions from arm_gic.c. Use arm_gic.c
as the refe
Add missing features to the Tegra GIC driver
In order to handle secure/non-secure interrupts, overload the plat_ic_*
functions and copy GIC helper functions from arm_gic.c. Use arm_gic.c
as the reference to add Tegra's GIC helper functions.
Now that Tegra has its own GIC implementation, we have no use for
plat_gic.c and arm_gic.c files.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 09aa0392 | 18-Jun-2015 |
danh-arm <dan.handley@arm.com> |
Merge pull request #319 from vwadekar/tegra-video-mem-aperture-v3
Reserve a Video Memory aperture in DRAM memory |
| 9a964510 | 10-Jun-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Reserve a Video Memory aperture in DRAM memory
This patch adds support to reserve a memory carveout region in the
DRAM on Tegra SoCs. The memory controller provides specific registers
to specify the
Reserve a Video Memory aperture in DRAM memory
This patch adds support to reserve a memory carveout region in the
DRAM on Tegra SoCs. The memory controller provides specific registers
to specify the aperture's base and size. This aperture can also be
changed dynamically in order to re-size the memory available for
DRM video playback. In case of the new aperture not overlapping
the previous one, the previous aperture has to be cleared before
setting up the new one. This means we do not "leak" any video data
to the NS world.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| dc7fdad2 | 05-Jun-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Boot Trusted OS' on Tegra SoCs
This patch adds support to run a Trusted OS during boot time. The
previous stage bootloader passes the entry point information in
the 'bl32_ep_info' structure, which i
Boot Trusted OS' on Tegra SoCs
This patch adds support to run a Trusted OS during boot time. The
previous stage bootloader passes the entry point information in
the 'bl32_ep_info' structure, which is passed over to the SPD.
The build system expects the dispatcher to be passed as an input
parameter using the 'SPD=<dispatcher>' option. The Tegra docs have
also been updated with this information.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 08438e24 | 19-May-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Support for NVIDIA's Tegra T210 SoCs
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given
Support for NVIDIA's Tegra T210 SoCs
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given point in time.
This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
also adds support to boot secondary CPUs, enter/exit core power states for
all CPUs in the slow/fast clusters. The support to switch between clusters
is still not available in this patch and would be available later.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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