xref: /rk3399_ARM-atf/bl2/bl2.ld.S (revision 94c672e77f5e39902e46c26cc38df313f9bc1e49) 
1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform_def.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35ENTRY(bl2_entrypoint)
36
37MEMORY {
38    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
39}
40
41
42SECTIONS
43{
44    . = BL2_BASE;
45    ASSERT(. == ALIGN(4096),
46           "BL2_BASE address is not aligned on a page boundary.")
47
48    ro . : {
49        __RO_START__ = .;
50        *bl2_entrypoint.o(.text*)
51        *(.text*)
52        *(.rodata*)
53
54        /* Ensure 8-byte alignment for descriptors and ensure inclusion */
55        . = ALIGN(8);
56        __PARSER_LIB_DESCS_START__ = .;
57        KEEP(*(.img_parser_lib_descs))
58        __PARSER_LIB_DESCS_END__ = .;
59
60        *(.vectors)
61        __RO_END_UNALIGNED__ = .;
62        /*
63         * Memory page(s) mapped to this section will be marked as
64         * read-only, executable.  No RW data from the next section must
65         * creep in.  Ensure the rest of the current memory page is unused.
66         */
67        . = NEXT(4096);
68        __RO_END__ = .;
69    } >RAM
70
71    .data . : {
72        __DATA_START__ = .;
73        *(.data*)
74        __DATA_END__ = .;
75    } >RAM
76
77    stacks (NOLOAD) : {
78        __STACKS_START__ = .;
79        *(tzfw_normal_stacks)
80        __STACKS_END__ = .;
81    } >RAM
82
83    /*
84     * The .bss section gets initialised to 0 at runtime.
85     * Its base address must be 16-byte aligned.
86     */
87    .bss : ALIGN(16) {
88        __BSS_START__ = .;
89        *(SORT_BY_ALIGNMENT(.bss*))
90        *(COMMON)
91        __BSS_END__ = .;
92    } >RAM
93
94    /*
95     * The xlat_table section is for full, aligned page tables (4K).
96     * Removing them from .bss avoids forcing 4K alignment on
97     * the .bss section and eliminates the unecessary zero init
98     */
99    xlat_table (NOLOAD) : {
100        *(xlat_table)
101    } >RAM
102
103#if USE_COHERENT_MEM
104    /*
105     * The base address of the coherent memory section must be page-aligned (4K)
106     * to guarantee that the coherent data are stored on their own pages and
107     * are not mixed with normal data.  This is required to set up the correct
108     * memory attributes for the coherent data page tables.
109     */
110    coherent_ram (NOLOAD) : ALIGN(4096) {
111        __COHERENT_RAM_START__ = .;
112        *(tzfw_coherent_mem)
113        __COHERENT_RAM_END_UNALIGNED__ = .;
114        /*
115         * Memory page(s) mapped to this section will be marked
116         * as device memory.  No other unexpected data must creep in.
117         * Ensure the rest of the current memory page is unused.
118         */
119        . = NEXT(4096);
120        __COHERENT_RAM_END__ = .;
121    } >RAM
122#endif
123
124    __BL2_END__ = .;
125
126    __BSS_SIZE__ = SIZEOF(.bss);
127
128#if USE_COHERENT_MEM
129    __COHERENT_RAM_UNALIGNED_SIZE__ =
130        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
131#endif
132
133    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
134}
135