1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <bl_common.h> 33 #include <debug.h> 34 #include <platform.h> 35 #include <platform_def.h> 36 #include <platform_tsp.h> 37 #include <spinlock.h> 38 #include <tsp.h> 39 #include "tsp_private.h" 40 41 42 /******************************************************************************* 43 * Lock to control access to the console 44 ******************************************************************************/ 45 spinlock_t console_lock; 46 47 /******************************************************************************* 48 * Per cpu data structure to populate parameters for an SMC in C code and use 49 * a pointer to this structure in assembler code to populate x0-x7 50 ******************************************************************************/ 51 static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT]; 52 53 /******************************************************************************* 54 * Per cpu data structure to keep track of TSP activity 55 ******************************************************************************/ 56 work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; 57 58 /******************************************************************************* 59 * The BL32 memory footprint starts with an RO sections and ends 60 * with the linker symbol __BL32_END__. Use it to find the memory size 61 ******************************************************************************/ 62 #define BL32_TOTAL_BASE (unsigned long)(&__RO_START__) 63 64 #define BL32_TOTAL_LIMIT (unsigned long)(&__BL32_END__) 65 66 static tsp_args_t *set_smc_args(uint64_t arg0, 67 uint64_t arg1, 68 uint64_t arg2, 69 uint64_t arg3, 70 uint64_t arg4, 71 uint64_t arg5, 72 uint64_t arg6, 73 uint64_t arg7) 74 { 75 uint64_t mpidr = read_mpidr(); 76 uint32_t linear_id; 77 tsp_args_t *pcpu_smc_args; 78 79 /* 80 * Return to Secure Monitor by raising an SMC. The results of the 81 * service are passed as an arguments to the SMC 82 */ 83 linear_id = platform_get_core_pos(mpidr); 84 pcpu_smc_args = &tsp_smc_args[linear_id]; 85 write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0); 86 write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1); 87 write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2); 88 write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3); 89 write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4); 90 write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5); 91 write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6); 92 write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7); 93 94 return pcpu_smc_args; 95 } 96 97 /******************************************************************************* 98 * TSP main entry point where it gets the opportunity to initialize its secure 99 * state/applications. Once the state is initialized, it must return to the 100 * SPD with a pointer to the 'tsp_vector_table' jump table. 101 ******************************************************************************/ 102 uint64_t tsp_main(void) 103 { 104 NOTICE("TSP: %s\n", version_string); 105 NOTICE("TSP: %s\n", build_message); 106 INFO("TSP: Total memory base : 0x%lx\n", BL32_TOTAL_BASE); 107 INFO("TSP: Total memory size : 0x%lx bytes\n", 108 BL32_TOTAL_LIMIT - BL32_TOTAL_BASE); 109 110 uint64_t mpidr = read_mpidr(); 111 uint32_t linear_id = platform_get_core_pos(mpidr); 112 113 /* Initialize the platform */ 114 tsp_platform_setup(); 115 116 /* Initialize secure/applications state here */ 117 tsp_generic_timer_start(); 118 119 /* Update this cpu's statistics */ 120 tsp_stats[linear_id].smc_count++; 121 tsp_stats[linear_id].eret_count++; 122 tsp_stats[linear_id].cpu_on_count++; 123 124 #if LOG_LEVEL >= LOG_LEVEL_INFO 125 spin_lock(&console_lock); 126 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", mpidr, 127 tsp_stats[linear_id].smc_count, 128 tsp_stats[linear_id].eret_count, 129 tsp_stats[linear_id].cpu_on_count); 130 spin_unlock(&console_lock); 131 #endif 132 return (uint64_t) &tsp_vector_table; 133 } 134 135 /******************************************************************************* 136 * This function performs any remaining book keeping in the test secure payload 137 * after this cpu's architectural state has been setup in response to an earlier 138 * psci cpu_on request. 139 ******************************************************************************/ 140 tsp_args_t *tsp_cpu_on_main(void) 141 { 142 uint64_t mpidr = read_mpidr(); 143 uint32_t linear_id = platform_get_core_pos(mpidr); 144 145 /* Initialize secure/applications state here */ 146 tsp_generic_timer_start(); 147 148 /* Update this cpu's statistics */ 149 tsp_stats[linear_id].smc_count++; 150 tsp_stats[linear_id].eret_count++; 151 tsp_stats[linear_id].cpu_on_count++; 152 153 #if LOG_LEVEL >= LOG_LEVEL_INFO 154 spin_lock(&console_lock); 155 INFO("TSP: cpu 0x%lx turned on\n", mpidr); 156 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", mpidr, 157 tsp_stats[linear_id].smc_count, 158 tsp_stats[linear_id].eret_count, 159 tsp_stats[linear_id].cpu_on_count); 160 spin_unlock(&console_lock); 161 #endif 162 /* Indicate to the SPD that we have completed turned ourselves on */ 163 return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0); 164 } 165 166 /******************************************************************************* 167 * This function performs any remaining book keeping in the test secure payload 168 * before this cpu is turned off in response to a psci cpu_off request. 169 ******************************************************************************/ 170 tsp_args_t *tsp_cpu_off_main(uint64_t arg0, 171 uint64_t arg1, 172 uint64_t arg2, 173 uint64_t arg3, 174 uint64_t arg4, 175 uint64_t arg5, 176 uint64_t arg6, 177 uint64_t arg7) 178 { 179 uint64_t mpidr = read_mpidr(); 180 uint32_t linear_id = platform_get_core_pos(mpidr); 181 182 /* 183 * This cpu is being turned off, so disable the timer to prevent the 184 * secure timer interrupt from interfering with power down. A pending 185 * interrupt will be lost but we do not care as we are turning off. 186 */ 187 tsp_generic_timer_stop(); 188 189 /* Update this cpu's statistics */ 190 tsp_stats[linear_id].smc_count++; 191 tsp_stats[linear_id].eret_count++; 192 tsp_stats[linear_id].cpu_off_count++; 193 194 #if LOG_LEVEL >= LOG_LEVEL_INFO 195 spin_lock(&console_lock); 196 INFO("TSP: cpu 0x%lx off request\n", mpidr); 197 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", mpidr, 198 tsp_stats[linear_id].smc_count, 199 tsp_stats[linear_id].eret_count, 200 tsp_stats[linear_id].cpu_off_count); 201 spin_unlock(&console_lock); 202 #endif 203 204 /* Indicate to the SPD that we have completed this request */ 205 return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); 206 } 207 208 /******************************************************************************* 209 * This function performs any book keeping in the test secure payload before 210 * this cpu's architectural state is saved in response to an earlier psci 211 * cpu_suspend request. 212 ******************************************************************************/ 213 tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, 214 uint64_t arg1, 215 uint64_t arg2, 216 uint64_t arg3, 217 uint64_t arg4, 218 uint64_t arg5, 219 uint64_t arg6, 220 uint64_t arg7) 221 { 222 uint64_t mpidr = read_mpidr(); 223 uint32_t linear_id = platform_get_core_pos(mpidr); 224 225 /* 226 * Save the time context and disable it to prevent the secure timer 227 * interrupt from interfering with wakeup from the suspend state. 228 */ 229 tsp_generic_timer_save(); 230 tsp_generic_timer_stop(); 231 232 /* Update this cpu's statistics */ 233 tsp_stats[linear_id].smc_count++; 234 tsp_stats[linear_id].eret_count++; 235 tsp_stats[linear_id].cpu_suspend_count++; 236 237 #if LOG_LEVEL >= LOG_LEVEL_INFO 238 spin_lock(&console_lock); 239 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", 240 mpidr, 241 tsp_stats[linear_id].smc_count, 242 tsp_stats[linear_id].eret_count, 243 tsp_stats[linear_id].cpu_suspend_count); 244 spin_unlock(&console_lock); 245 #endif 246 247 /* Indicate to the SPD that we have completed this request */ 248 return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0); 249 } 250 251 /******************************************************************************* 252 * This function performs any book keeping in the test secure payload after this 253 * cpu's architectural state has been restored after wakeup from an earlier psci 254 * cpu_suspend request. 255 ******************************************************************************/ 256 tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level, 257 uint64_t arg1, 258 uint64_t arg2, 259 uint64_t arg3, 260 uint64_t arg4, 261 uint64_t arg5, 262 uint64_t arg6, 263 uint64_t arg7) 264 { 265 uint64_t mpidr = read_mpidr(); 266 uint32_t linear_id = platform_get_core_pos(mpidr); 267 268 /* Restore the generic timer context */ 269 tsp_generic_timer_restore(); 270 271 /* Update this cpu's statistics */ 272 tsp_stats[linear_id].smc_count++; 273 tsp_stats[linear_id].eret_count++; 274 tsp_stats[linear_id].cpu_resume_count++; 275 276 #if LOG_LEVEL >= LOG_LEVEL_INFO 277 spin_lock(&console_lock); 278 INFO("TSP: cpu 0x%lx resumed. suspend level %ld\n", 279 mpidr, suspend_level); 280 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", 281 mpidr, 282 tsp_stats[linear_id].smc_count, 283 tsp_stats[linear_id].eret_count, 284 tsp_stats[linear_id].cpu_suspend_count); 285 spin_unlock(&console_lock); 286 #endif 287 /* Indicate to the SPD that we have completed this request */ 288 return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0); 289 } 290 291 /******************************************************************************* 292 * This function performs any remaining bookkeeping in the test secure payload 293 * before the system is switched off (in response to a psci SYSTEM_OFF request) 294 ******************************************************************************/ 295 tsp_args_t *tsp_system_off_main(uint64_t arg0, 296 uint64_t arg1, 297 uint64_t arg2, 298 uint64_t arg3, 299 uint64_t arg4, 300 uint64_t arg5, 301 uint64_t arg6, 302 uint64_t arg7) 303 { 304 uint64_t mpidr = read_mpidr(); 305 uint32_t linear_id = platform_get_core_pos(mpidr); 306 307 /* Update this cpu's statistics */ 308 tsp_stats[linear_id].smc_count++; 309 tsp_stats[linear_id].eret_count++; 310 311 #if LOG_LEVEL >= LOG_LEVEL_INFO 312 spin_lock(&console_lock); 313 INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", mpidr); 314 INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", mpidr, 315 tsp_stats[linear_id].smc_count, 316 tsp_stats[linear_id].eret_count); 317 spin_unlock(&console_lock); 318 #endif 319 320 /* Indicate to the SPD that we have completed this request */ 321 return set_smc_args(TSP_SYSTEM_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); 322 } 323 324 /******************************************************************************* 325 * This function performs any remaining bookkeeping in the test secure payload 326 * before the system is reset (in response to a psci SYSTEM_RESET request) 327 ******************************************************************************/ 328 tsp_args_t *tsp_system_reset_main(uint64_t arg0, 329 uint64_t arg1, 330 uint64_t arg2, 331 uint64_t arg3, 332 uint64_t arg4, 333 uint64_t arg5, 334 uint64_t arg6, 335 uint64_t arg7) 336 { 337 uint64_t mpidr = read_mpidr(); 338 uint32_t linear_id = platform_get_core_pos(mpidr); 339 340 /* Update this cpu's statistics */ 341 tsp_stats[linear_id].smc_count++; 342 tsp_stats[linear_id].eret_count++; 343 344 #if LOG_LEVEL >= LOG_LEVEL_INFO 345 spin_lock(&console_lock); 346 INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", mpidr); 347 INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", mpidr, 348 tsp_stats[linear_id].smc_count, 349 tsp_stats[linear_id].eret_count); 350 spin_unlock(&console_lock); 351 #endif 352 353 /* Indicate to the SPD that we have completed this request */ 354 return set_smc_args(TSP_SYSTEM_RESET_DONE, 0, 0, 0, 0, 0, 0, 0); 355 } 356 357 /******************************************************************************* 358 * TSP fast smc handler. The secure monitor jumps to this function by 359 * doing the ERET after populating X0-X7 registers. The arguments are received 360 * in the function arguments in order. Once the service is rendered, this 361 * function returns to Secure Monitor by raising SMC. 362 ******************************************************************************/ 363 tsp_args_t *tsp_smc_handler(uint64_t func, 364 uint64_t arg1, 365 uint64_t arg2, 366 uint64_t arg3, 367 uint64_t arg4, 368 uint64_t arg5, 369 uint64_t arg6, 370 uint64_t arg7) 371 { 372 uint64_t results[2]; 373 uint64_t service_args[2]; 374 uint64_t mpidr = read_mpidr(); 375 uint32_t linear_id = platform_get_core_pos(mpidr); 376 377 /* Update this cpu's statistics */ 378 tsp_stats[linear_id].smc_count++; 379 tsp_stats[linear_id].eret_count++; 380 381 INFO("TSP: cpu 0x%lx received %s smc 0x%lx\n", mpidr, 382 ((func >> 31) & 1) == 1 ? "fast" : "standard", 383 func); 384 INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", mpidr, 385 tsp_stats[linear_id].smc_count, 386 tsp_stats[linear_id].eret_count); 387 388 /* Render secure services and obtain results here */ 389 results[0] = arg1; 390 results[1] = arg2; 391 392 /* 393 * Request a service back from dispatcher/secure monitor. This call 394 * return and thereafter resume exectuion 395 */ 396 tsp_get_magic(service_args); 397 398 /* Determine the function to perform based on the function ID */ 399 switch (TSP_BARE_FID(func)) { 400 case TSP_ADD: 401 results[0] += service_args[0]; 402 results[1] += service_args[1]; 403 break; 404 case TSP_SUB: 405 results[0] -= service_args[0]; 406 results[1] -= service_args[1]; 407 break; 408 case TSP_MUL: 409 results[0] *= service_args[0]; 410 results[1] *= service_args[1]; 411 break; 412 case TSP_DIV: 413 results[0] /= service_args[0] ? service_args[0] : 1; 414 results[1] /= service_args[1] ? service_args[1] : 1; 415 break; 416 default: 417 break; 418 } 419 420 return set_smc_args(func, 0, 421 results[0], 422 results[1], 423 0, 0, 0, 0); 424 } 425 426