1/* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <cortex_a57.h> 35#include <v2m_def.h> 36#include "../juno_def.h" 37 38 39 .globl plat_reset_handler 40 41 42 /* -------------------------------------------------------------------- 43 * void plat_reset_handler(void); 44 * 45 * Before adding code in this function, refer to the guidelines in 46 * docs/firmware-design.md to determine whether the code should reside 47 * within the FIRST_RESET_HANDLER_CALL block or not. 48 * 49 * For Juno r0: 50 * - Implement workaround for defect id 831273 by enabling an event 51 * stream every 65536 cycles. 52 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 53 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 54 * 55 * For Juno r1: 56 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 57 * Note that: 58 * - The default value for the L2 Tag RAM latency for Cortex-A57 is 59 * suitable. 60 * - Defect #831273 doesn't affect Juno r1. 61 * 62 * This code is included only when FIRST_RESET_HANDLER_CALL is defined 63 * since it should be executed only during BL1. 64 * -------------------------------------------------------------------- 65 */ 66func plat_reset_handler 67#ifdef FIRST_RESET_HANDLER_CALL 68 /* -------------------------------------------------------------------- 69 * Determine whether this code is running on Juno r0 or Juno r1. 70 * Keep this information in x2. 71 * -------------------------------------------------------------------- 72 */ 73 /* Read the V2M SYS_ID register */ 74 mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID) 75 ldr w1, [x0] 76 /* Extract board revision from the SYS_ID */ 77 ubfx x1, x1, #V2M_SYS_ID_REV_SHIFT, #4 78 /* 79 * On Juno R0: x2 := REV_JUNO_R0 - 1 = 0 80 * On Juno R1: x2 := REV_JUNO_R1 - 1 = 1 81 */ 82 sub x2, x1, #1 83 84 /* -------------------------------------------------------------------- 85 * Determine whether this code is executed on a Cortex-A53 or on a 86 * Cortex-A57 core. 87 * -------------------------------------------------------------------- 88 */ 89 mrs x0, midr_el1 90 ubfx x1, x0, MIDR_PN_SHIFT, #12 91 cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 92 b.eq A57 93 94 /* Nothing needs to be done for the Cortex-A53 on Juno r1 */ 95 cbz x2, apply_831273 96 ret 97 98A57: 99 /* -------------------------------------------------------------------- 100 * Cortex-A57 specific settings 101 * -------------------------------------------------------------------- 102 */ 103 104 /* Change the L2 Data RAM latency to 3 cycles */ 105 mov x0, #L2_DATA_RAM_LATENCY_3_CYCLES 106 cbnz x2, apply_l2_ram_latencies 107 /* On Juno r0, also change the L2 Tag RAM latency to 3 cycles */ 108 orr x0, x0, #(L2_TAG_RAM_LATENCY_3_CYCLES << \ 109 L2CTLR_TAG_RAM_LATENCY_SHIFT) 110apply_l2_ram_latencies: 111 msr L2CTLR_EL1, x0 112 113 /* Juno r1 doesn't suffer from defect #831273 */ 114 cbnz x2, ret 115 116apply_831273: 117 /* -------------------------------------------------------------------- 118 * On Juno r0, enable the event stream every 65536 cycles 119 * -------------------------------------------------------------------- 120 */ 121 mov x0, #(0xf << EVNTI_SHIFT) 122 orr x0, x0, #EVNTEN_BIT 123 msr CNTKCTL_EL1, x0 124ret: 125 isb 126#endif /* FIRST_RESET_HANDLER_CALL */ 127 ret 128endfunc plat_reset_handler 129