1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl31.h> 35 #include <bl_common.h> 36 #include <console.h> 37 #include <cortex_a57.h> 38 #include <cortex_a53.h> 39 #include <debug.h> 40 #include <memctrl.h> 41 #include <mmio.h> 42 #include <platform.h> 43 #include <platform_def.h> 44 #include <stddef.h> 45 #include <tegra_private.h> 46 47 /******************************************************************************* 48 * Declarations of linker defined symbols which will help us find the layout 49 * of trusted SRAM 50 ******************************************************************************/ 51 extern unsigned long __RO_START__; 52 extern unsigned long __RO_END__; 53 extern unsigned long __BL31_END__; 54 55 #if USE_COHERENT_MEM 56 extern unsigned long __COHERENT_RAM_START__; 57 extern unsigned long __COHERENT_RAM_END__; 58 #endif 59 60 extern uint64_t tegra_bl31_phys_base; 61 62 /* 63 * The next 3 constants identify the extents of the code, RO data region and the 64 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 65 * therefore they must be page-aligned. It is the responsibility of the linker 66 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 67 * refer to page-aligned addresses. 68 */ 69 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 70 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 71 #define BL31_END (unsigned long)(&__BL31_END__) 72 73 #if USE_COHERENT_MEM 74 /* 75 * The next 2 constants identify the extents of the coherent memory region. 76 * These addresses are used by the MMU setup code and therefore they must be 77 * page-aligned. It is the responsibility of the linker script to ensure that 78 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols 79 * refer to page-aligned addresses. 80 */ 81 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 82 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 83 #endif 84 85 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 86 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 87 (uint64_t)TZDRAM_SIZE, (uintptr_t)NULL 88 }; 89 90 /******************************************************************************* 91 * This variable holds the non-secure image entry address 92 ******************************************************************************/ 93 extern uint64_t ns_image_entrypoint; 94 95 /******************************************************************************* 96 * Return a pointer to the 'entry_point_info' structure of the next image for 97 * security state specified. BL33 corresponds to the non-secure image type 98 * while BL32 corresponds to the secure image type. 99 ******************************************************************************/ 100 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 101 { 102 if (type == NON_SECURE) 103 return &bl33_image_ep_info; 104 105 if (type == SECURE) 106 return &bl32_image_ep_info; 107 108 return NULL; 109 } 110 111 /******************************************************************************* 112 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 113 * passes this platform specific information. 114 ******************************************************************************/ 115 plat_params_from_bl2_t *bl31_get_plat_params(void) 116 { 117 return &plat_bl31_params_from_bl2; 118 } 119 120 /******************************************************************************* 121 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 122 * info. 123 ******************************************************************************/ 124 void bl31_early_platform_setup(bl31_params_t *from_bl2, 125 void *plat_params_from_bl2) 126 { 127 plat_params_from_bl2_t *plat_params = 128 (plat_params_from_bl2_t *)plat_params_from_bl2; 129 130 /* 131 * Configure the UART port to be used as the console 132 */ 133 console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ, 134 TEGRA_CONSOLE_BAUDRATE); 135 136 /* Initialise crash console */ 137 plat_crash_console_init(); 138 139 /* 140 * Copy BL3-3, BL3-2 entry point information. 141 * They are stored in Secure RAM, in BL2's address space. 142 */ 143 bl33_image_ep_info = *from_bl2->bl33_ep_info; 144 bl32_image_ep_info = *from_bl2->bl32_ep_info; 145 146 /* 147 * Parse platform specific parameters - TZDRAM aperture size and 148 * pointer to BL32 params. 149 */ 150 if (plat_params) { 151 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 152 plat_bl31_params_from_bl2.bl32_params = plat_params->bl32_params; 153 } 154 } 155 156 /******************************************************************************* 157 * Initialize the gic, configure the SCR. 158 ******************************************************************************/ 159 void bl31_platform_setup(void) 160 { 161 uint32_t tmp_reg; 162 163 /* 164 * Setup secondary CPU POR infrastructure. 165 */ 166 plat_secondary_setup(); 167 168 /* 169 * Initial Memory Controller configuration. 170 */ 171 tegra_memctrl_setup(); 172 173 /* 174 * Do initial security configuration to allow DRAM/device access. 175 */ 176 tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, 177 plat_bl31_params_from_bl2.tzdram_size); 178 179 /* Set the next EL to be AArch64 */ 180 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 181 write_scr(tmp_reg); 182 183 /* Initialize the gic cpu and distributor interfaces */ 184 tegra_gic_setup(); 185 } 186 187 /******************************************************************************* 188 * Perform the very early platform specific architectural setup here. At the 189 * moment this only intializes the mmu in a quick and dirty way. 190 ******************************************************************************/ 191 void bl31_plat_arch_setup(void) 192 { 193 unsigned long bl31_base_pa = tegra_bl31_phys_base; 194 unsigned long total_base = bl31_base_pa; 195 unsigned long total_size = TZDRAM_END - BL31_RO_BASE; 196 unsigned long ro_start = bl31_base_pa; 197 unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE; 198 unsigned long coh_start = 0; 199 unsigned long coh_size = 0; 200 const mmap_region_t *plat_mmio_map = NULL; 201 202 #if USE_COHERENT_MEM 203 coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE); 204 coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE; 205 #endif 206 207 /* add memory regions */ 208 mmap_add_region(total_base, total_base, 209 total_size, 210 MT_MEMORY | MT_RW | MT_SECURE); 211 mmap_add_region(ro_start, ro_start, 212 ro_size, 213 MT_MEMORY | MT_RO | MT_SECURE); 214 #if USE_COHERENT_MEM 215 mmap_add_region(coh_start, coh_start, 216 coh_size, 217 MT_DEVICE | MT_RW | MT_SECURE); 218 #endif 219 220 /* add MMIO space */ 221 plat_mmio_map = plat_get_mmio_map(); 222 if (plat_mmio_map) 223 mmap_add(plat_mmio_map); 224 else 225 WARN("MMIO map not available\n"); 226 227 /* set up translation tables */ 228 init_xlat_tables(); 229 230 /* enable the MMU */ 231 enable_mmu_el3(0); 232 } 233