1/* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <gic_v2.h> 34#include <platform_def.h> 35#include <v2m_def.h> 36#include "../drivers/pwrc/fvp_pwrc.h" 37#include "../fvp_def.h" 38 39 .globl plat_secondary_cold_boot_setup 40 .globl platform_get_entrypoint 41 .globl platform_mem_init 42 .globl platform_is_primary_cpu 43 44 .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res 45 ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID 46 ldr \w_tmp, [\x_tmp] 47 ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH 48 cmp \w_tmp, #BLD_GIC_VE_MMAP 49 csel \res, \param1, \param2, eq 50 .endm 51 52 /* ----------------------------------------------------- 53 * void plat_secondary_cold_boot_setup (void); 54 * 55 * This function performs any platform specific actions 56 * needed for a secondary cpu after a cold reset e.g 57 * mark the cpu's presence, mechanism to place it in a 58 * holding pen etc. 59 * TODO: Should we read the PSYS register to make sure 60 * that the request has gone through. 61 * ----------------------------------------------------- 62 */ 63func plat_secondary_cold_boot_setup 64 /* --------------------------------------------- 65 * Power down this cpu. 66 * TODO: Do we need to worry about powering the 67 * cluster down as well here. That will need 68 * locks which we won't have unless an elf- 69 * loader zeroes out the zi section. 70 * --------------------------------------------- 71 */ 72 mrs x0, mpidr_el1 73 ldr x1, =PWRC_BASE 74 str w0, [x1, #PPOFFR_OFF] 75 76 /* --------------------------------------------- 77 * Deactivate the gic cpu interface as well 78 * --------------------------------------------- 79 */ 80 ldr x0, =VE_GICC_BASE 81 ldr x1, =BASE_GICC_BASE 82 fvp_choose_gicmmap x0, x1, x2, w2, x1 83 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) 84 orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) 85 str w0, [x1, #GICC_CTLR] 86 87 /* --------------------------------------------- 88 * There is no sane reason to come out of this 89 * wfi so panic if we do. This cpu will be pow- 90 * ered on and reset by the cpu_on pm api 91 * --------------------------------------------- 92 */ 93 dsb sy 94 wfi 95cb_panic: 96 b cb_panic 97endfunc plat_secondary_cold_boot_setup 98 99 100 /* ----------------------------------------------------- 101 * void platform_get_entrypoint (unsigned int mpid); 102 * 103 * Main job of this routine is to distinguish between 104 * a cold and warm boot. 105 * On a cold boot the secondaries first wait for the 106 * platform to be initialized after which they are 107 * hotplugged in. The primary proceeds to perform the 108 * platform initialization. 109 * On a warm boot, each cpu jumps to the address in its 110 * mailbox. 111 * 112 * TODO: Not a good idea to save lr in a temp reg 113 * TODO: PSYSR is a common register and should be 114 * accessed using locks. Since its not possible 115 * to use locks immediately after a cold reset 116 * we are relying on the fact that after a cold 117 * reset all cpus will read the same WK field 118 * ----------------------------------------------------- 119 */ 120func platform_get_entrypoint 121 mov x9, x30 // lr 122 mov x2, x0 123 ldr x1, =PWRC_BASE 124 str w2, [x1, #PSYSR_OFF] 125 ldr w2, [x1, #PSYSR_OFF] 126 ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_MASK 127 cmp w2, #WKUP_PPONR 128 beq warm_reset 129 cmp w2, #WKUP_GICREQ 130 beq warm_reset 131 mov x0, #0 132 b exit 133warm_reset: 134 /* --------------------------------------------- 135 * A per-cpu mailbox is maintained in the tru- 136 * sted DRAM. Its flushed out of the caches 137 * after every update using normal memory so 138 * its safe to read it here with SO attributes 139 * --------------------------------------------- 140 */ 141 ldr x10, =MBOX_BASE 142 bl platform_get_core_pos 143 lsl x0, x0, #ARM_CACHE_WRITEBACK_SHIFT 144 ldr x0, [x10, x0] 145 cbz x0, _panic 146exit: 147 ret x9 148_panic: b _panic 149endfunc platform_get_entrypoint 150 151 152 /* ----------------------------------------------------- 153 * void platform_mem_init (void); 154 * 155 * Zero out the mailbox registers in the shared memory. 156 * The mmu is turned off right now and only the primary can 157 * ever execute this code. Secondaries will read the 158 * mailboxes using SO accesses. In short, BL31 will 159 * update the mailboxes after mapping the tzdram as 160 * normal memory. It will flush its copy after update. 161 * BL1 will always read the mailboxes with the MMU off 162 * ----------------------------------------------------- 163 */ 164func platform_mem_init 165 ldr x0, =MBOX_BASE 166 mov w1, #PLATFORM_CORE_COUNT 167loop: 168 str xzr, [x0], #CACHE_WRITEBACK_GRANULE 169 subs w1, w1, #1 170 b.gt loop 171 ret 172endfunc platform_mem_init 173 174 175func platform_is_primary_cpu 176 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 177 cmp x0, #FVP_PRIMARY_CPU 178 cset x0, eq 179 ret 180endfunc platform_is_primary_cpu 181