1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #define PLAT_PRIMARY_CPU 0x0 11 12 #define MT_GIC_BASE (0x0C000000) 13 #define MCUCFG_BASE (0x0C530000) 14 #define IO_PHYS (0x10000000) 15 16 /* Aggregate of all devices for MMU mapping */ 17 #define MTK_DEV_RNG0_BASE IO_PHYS 18 #define MTK_DEV_RNG0_SIZE 0x10000000 19 #define MTK_DEV_RNG2_BASE MT_GIC_BASE 20 #define MTK_DEV_RNG2_SIZE 0x600000 21 #define MTK_MCDI_SRAM_BASE 0x11B000 22 #define MTK_MCDI_SRAM_MAP_SIZE 0x1000 23 24 #define SPM_BASE (IO_PHYS + 0x00006000) 25 26 /******************************************************************************* 27 * DP/eDP related constants 28 ******************************************************************************/ 29 #define eDP_SEC_BASE (IO_PHYS + 0x0C504000) 30 #define DP_SEC_BASE (IO_PHYS + 0x0C604000) 31 #define eDP_SEC_SIZE 0x1000 32 #define DP_SEC_SIZE 0x1000 33 34 /******************************************************************************* 35 * GPIO related constants 36 ******************************************************************************/ 37 #define GPIO_BASE (IO_PHYS + 0x00005000) 38 #define IOCFG_BM_BASE (IO_PHYS + 0x01D10000) 39 #define IOCFG_BL_BASE (IO_PHYS + 0x01D30000) 40 #define IOCFG_BR_BASE (IO_PHYS + 0x01D40000) 41 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 42 #define IOCFG_RB_BASE (IO_PHYS + 0x01EB0000) 43 #define IOCFG_TL_BASE (IO_PHYS + 0x01F40000) 44 45 /******************************************************************************* 46 * UART related constants 47 ******************************************************************************/ 48 #define UART0_BASE (IO_PHYS + 0x01001100) 49 #define UART1_BASE (IO_PHYS + 0x01001200) 50 51 #define UART_BAUDRATE 115200 52 53 /******************************************************************************* 54 * PMIC related constants 55 ******************************************************************************/ 56 #define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) 57 58 /******************************************************************************* 59 * System counter frequency related constants 60 ******************************************************************************/ 61 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 62 #define SYS_COUNTER_FREQ_IN_MHZ 13 63 64 /******************************************************************************* 65 * GIC-600 & interrupt handling related constants 66 ******************************************************************************/ 67 /* Base MTK_platform compatible GIC memory map */ 68 #define BASE_GICD_BASE MT_GIC_BASE 69 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 70 71 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 72 #define CIRQ_REG_NUM 23 73 #define CIRQ_IRQ_NUM 730 74 #define CIRQ_SPI_START 96 75 #define MD_WDT_IRQ_BIT_ID 141 76 /******************************************************************************* 77 * Platform binary types for linking 78 ******************************************************************************/ 79 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 80 #define PLATFORM_LINKER_ARCH aarch64 81 82 /******************************************************************************* 83 * Generic platform constants 84 ******************************************************************************/ 85 #define PLATFORM_STACK_SIZE 0x800 86 87 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 88 89 #define PLAT_MAX_PWR_LVL U(3) 90 #define PLAT_MAX_RET_STATE U(1) 91 #define PLAT_MAX_OFF_STATE U(9) 92 93 #define PLATFORM_SYSTEM_COUNT U(1) 94 #define PLATFORM_MCUSYS_COUNT U(1) 95 #define PLATFORM_CLUSTER_COUNT U(1) 96 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 97 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 98 99 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 100 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 101 102 #define SOC_CHIP_ID U(0x8195) 103 104 /******************************************************************************* 105 * Platform memory map related constants 106 ******************************************************************************/ 107 #define TZRAM_BASE 0x54600000 108 #define TZRAM_SIZE 0x00030000 109 110 /******************************************************************************* 111 * BL31 specific defines. 112 ******************************************************************************/ 113 /* 114 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 115 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 116 * little space for growth. 117 */ 118 #define BL31_BASE (TZRAM_BASE + 0x1000) 119 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 120 121 /******************************************************************************* 122 * Platform specific page table and MMU setup constants 123 ******************************************************************************/ 124 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 125 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 126 #define MAX_XLAT_TABLES 16 127 #define MAX_MMAP_REGIONS 16 128 129 /******************************************************************************* 130 * Declarations and constants to access the mailboxes safely. Each mailbox is 131 * aligned on the biggest cache line size in the platform. This is known only 132 * to the platform as it might have a combination of integrated and external 133 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 134 * line at any cache level. They could belong to different cpus/clusters & 135 * get written while being protected by different locks causing corruption of 136 * a valid mailbox address. 137 ******************************************************************************/ 138 #define CACHE_WRITEBACK_SHIFT 6 139 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 140 #endif /* PLATFORM_DEF_H */ 141