refactor(mediatek): move headers to common folder

The plat_macros.S and plat_private.h are identical across some
platforms, moved to the common folder for easier maintenance.

Change-Id: I31c71551aa

refactor(mediatek): move headers to common folder

The plat_macros.S and plat_private.h are identical across some
platforms, moved to the common folder for easier maintenance.

Change-Id: I31c71551aa0e891f080e58f21e6e79551d2a19e0
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A. The current workaround attempts to follow option 2 but
misapplies it. Specifically, it statically sets PF_MODE to
conservative, which is not the recommended approach. According to the
erratum documentation, PF_MODE should be configured in conservative
mode only when we disable data prefetcher however this is not done
in TF-A and thus the workaround is not needed in TF-A.

The static setting of PF_MODE in TF-A does not correctly address the
erratum and may introduce unnecessary performance degradation on
platforms that adopt it without fully understanding its implications.

To prevent incorrect or unintended use, the current implementation of
this erratum workaround should be removed from TF-A and not adopted by
platforms.

List of Impacted CPU's with Errata Numbers and reference to SDEN -

Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest
Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest
Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest
Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest
Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest
Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest
Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest
Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(mediatek): move plat_helpers.h to the common folder

The plat_helpers.h is identical across various platforms, moved to the
common folder for easier maintenance.

Change-Id: Ic9f10c697fcda7e3cfb

feat(mediatek): move plat_helpers.h to the common folder

The plat_helpers.h is identical across various platforms, moved to the
common folder for easier maintenance.

Change-Id: Ic9f10c697fcda7e3cfbf32e67486c9cd28481b8a
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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feat(mt8188): add MT8188 TRNG driver

Add MTK TRNG driver for MT8188.

Change-Id: I604edd42ffce9a153e209a015ba454b51da454e1
Signed-off-by: Suyuan Su <suyuan.su@mediatek.com>
Signed-off-by: Gavin Liu

feat(mt8188): add MT8188 TRNG driver

Add MTK TRNG driver for MT8188.

Change-Id: I604edd42ffce9a153e209a015ba454b51da454e1
Signed-off-by: Suyuan Su <suyuan.su@mediatek.com>
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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feat(mediatek): configure DEV_IRQ as G1S interrupt

In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK

feat(mediatek): configure DEV_IRQ as G1S interrupt

In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK GIC driver to configure the interrupt properly.

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Change-Id: Id909a42b535088c6d0dcaf803d3f2faf312ae846

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feat(mt8188): add secure iommu support

The secure IOMMU has two secure banks: VDO and VPP. Add SiP call to
report the secure bank status in debug build.
About more background, please see:
https://gi

feat(mt8188): add secure iommu support

The secure IOMMU has two secure banks: VDO and VPP. Add SiP call to
report the secure bank status in debug build.
About more background, please see:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/include/dt-bindings/memory/mediatek,mt8188-memory-port.h?id=d5cda142d649c690fb0fcf1e29f3df63fbafc442

Change-Id: I7b3319e84391fc6d7f456659f8b8c5d9d1c6ab9d
Signed-off-by: Anan Sun <anan.sun@mediatek.corp-partner.google.com>
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>

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feat(mt8188): add devapc setting of apusys rcx

Apusys rcx is a subsys in apusys, and it is a basic domain of APU and
it connects several components in APU.
The devapc control of apusys rcx is also i

feat(mt8188): add devapc setting of apusys rcx

Apusys rcx is a subsys in apusys, and it is a basic domain of APU and
it connects several components in APU.
The devapc control of apusys rcx is also inside APU and it can only be
set when APU is powered on.
Then apusys kernel driver will trigger rcx devapc init by ATF smc call.

Change-Id: If4249f22a08690b1e4f5aa5f0cbfb54ccacf90e1
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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feat(mediatek): add APU bootup control smc call

Add APU bootup control smc call.
The steps of bootup flow:
1. set up APU config.
2. reset APU.
3. set up APU boot config.
4. boot APU.

Change

feat(mediatek): add APU bootup control smc call

Add APU bootup control smc call.
The steps of bootup flow:
1. set up APU config.
2. reset APU.
3. set up APU boot config.
4. boot APU.

Change-Id: I9e930070a64c7c4dcaa3a8b3d28b897823e9f53c
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8188): enable apusys mailbox mpu protect

Enable apusys mailbox mpu protect.

Change-Id: Idbf67084037b7ecf4926f57a901075f98540ee57
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by:

feat(mt8188): enable apusys mailbox mpu protect

Enable apusys mailbox mpu protect.

Change-Id: Idbf67084037b7ecf4926f57a901075f98540ee57
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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feat(mt8188): enable apusys domain remap

Enable apusys domain remap to protect no-protect memory.
- Remap request which from domain 5 to domain 14.
- Remap request which from domain 7 to domain

feat(mt8188): enable apusys domain remap

Enable apusys domain remap to protect no-protect memory.
- Remap request which from domain 5 to domain 14.
- Remap request which from domain 7 to domain 14.

Change-Id: Iccd188e3b8edbe916fa9767c841a844b66c6011f
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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feat(mt8188): add apusys ao devapc setting

Apusys ao devapc is a set of control registers inside APU, and it
controls the access permission of APU ao domain.
Moreover, apusys ao devapc must be set a

feat(mt8188): add apusys ao devapc setting

Apusys ao devapc is a set of control registers inside APU, and it
controls the access permission of APU ao domain.
Moreover, apusys ao devapc must be set after apusys power init, so
we need to place the drivers in TF-A instead of coreboot.

Change-Id: Ife849c32d4dd9dca15432d4b8a51753fde61b148
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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feat(mt8188): increase TZRAM_SIZE from 192KB to 256KB

Increase TZRAM_SIZE to 256KB for MT8188 APUSYS.

Change-Id: Iabe1a4aeb79ba23c3e963170a8eb9ce19f2925f3
Signed-off-by: Karl Li <karl.li@mediatek.c

feat(mt8188): increase TZRAM_SIZE from 192KB to 256KB

Increase TZRAM_SIZE to 256KB for MT8188 APUSYS.

Change-Id: Iabe1a4aeb79ba23c3e963170a8eb9ce19f2925f3
Signed-off-by: Karl Li <karl.li@mediatek.com>

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