| e231f3a5 | 19-Sep-2019 |
Usama Arif <usama.arif@arm.com> |
a5ds: Hold the secondary cpus in pen rather than panic
For the secondary CPUs, hold the cpu in wfe rather then panic.
This will be needed when multicore support is added to a5ds as
the smc call will
a5ds: Hold the secondary cpus in pen rather than panic
For the secondary CPUs, hold the cpu in wfe rather then panic.
This will be needed when multicore support is added to a5ds as
the smc call will write to the hold base and signal an event to
power on the secondary CPUs.
Change-Id: I0ffc2059e9ef894c21375ca5c94def859bfa6599
Signed-off-by: Usama Arif <usama.arif@arm.com>
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| cd3c5b4c | 13-Aug-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Modify FVP makefile for cores that support both AArch64/32
Some cores support only AArch64 from EL1 and above, e.g. A76, N1 etc. If
TF-A is compiled with CTX_INCLUDE_AARCH32_REGS=0 so as to properly
Modify FVP makefile for cores that support both AArch64/32
Some cores support only AArch64 from EL1 and above, e.g. A76, N1 etc. If
TF-A is compiled with CTX_INCLUDE_AARCH32_REGS=0 so as to properly
handle those cores, only the AArch64 cores' assembly is included in the
TF-A binary. In other words, for FVP, TF-A assumes that AArch64 only
cores will never exist in the same cluster with cores that also support
AArch32.
However, A55 and A75 can be used as AArch64 only cores, despite
supporting AArch32, too. This patch enables A55 and A75 to exist in
clusters together with AArch64 cores.
Change-Id: I58750ad6c3d76ce77eb354784c2a42f2c179031d
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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|
| 44e8d5eb | 20-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "plat/arm: Introduce corstone700 platform." into integration |
| 7bdc4698 | 28-Nov-2018 |
Manish Pandey <manish.pandey2@arm.com> |
plat/arm: Introduce corstone700 platform.
This patch adds support for Corstone-700 foundation IP, which integrates
both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible
subsystem.
Thi
plat/arm: Introduce corstone700 platform.
This patch adds support for Corstone-700 foundation IP, which integrates
both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible
subsystem.
This is an example implementation of Corstone-700 IP host firmware.
Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as
bringing Host out RESET. Host will start execution directly from BL32 and
then will jump to Linux.
It is an initial port and additional features are expected to be added
later.
Change-Id: I7b5c0278243d574284b777b2408375d007a7736e
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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|
| 988cc820 | 16-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "FVP: Add Delay Timer driver to BL1 and BL31" into integration |
| 1b597c22 | 16-Aug-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
FVP: Add Delay Timer driver to BL1 and BL31
SMMUv3 driver functions which are called from BL1 and BL31
currently use counter-based poll method for testing status
bits. Adding Delay Timer driver to B
FVP: Add Delay Timer driver to BL1 and BL31
SMMUv3 driver functions which are called from BL1 and BL31
currently use counter-based poll method for testing status
bits. Adding Delay Timer driver to BL1 and BL31 is required
for timeout-based implementation using timer delay functions
for SMMU and other drivers.
This patch adds new function `fvp_timer_init()` which
initialises either System level generic or SP804 timer based on
FVP_USE_SP804_TIMER build flag.
In BL2U `bl2u_early_platform_setup()` function the call to
`arm_bl2u_early_platform_setup()` (which calls
`generic_delay_timer_init()` ignoring FVP_USE_SP804_TIMER flag),
is replaced with `arm_console_boot_init()` and `fvp_timer_init()`.
Change-Id: Ifd8dcebf4019e877b9bc5641551deef77a44c0d1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| 300df53b | 16-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge changes from topic "lm/juno_dyn_cfg" into integration
* changes:
Juno: Use shared mbedtls heap between bl1 and bl2
Juno: add basic support for dynamic config |
| 9580f9bd | 31-Jul-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Juno: Use shared mbedtls heap between bl1 and bl2
Change-Id: Ia1ecad58ebf9de3f3a44b17ad1de57424b431125
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
| 8075fc59 | 29-Jul-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Juno: add basic support for dynamic config
Add the disable_auth dynamic parameter, that allows to disable the
authentication when TBBR is enabled. This parameter is for development
only.
Change-Id:
Juno: add basic support for dynamic config
Add the disable_auth dynamic parameter, that allows to disable the
authentication when TBBR is enabled. This parameter is for development
only.
Change-Id: Ic24ad16738517f7e07c4f506dcf69a1ae8df7d2d
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| 402b3cf8 | 09-Jul-2019 |
Julius Werner <jwerner@chromium.org> |
Switch AARCH32/AARCH64 to __aarch64__
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.
All common C compilers pre-define the same macros to signal which
architecture the cod
Switch AARCH32/AARCH64 to __aarch64__
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.
All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)
Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>
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|
| 66c1dafc | 26-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "sgm775: Fix build fail for TSP support on sgm775" into integration |
| 86126439 | 25-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "gby/cryptocell-multi-vers" into integration
* changes:
cryptocell: add product version awareness support
cryptocell: move Cryptocell specific API into driver |
| 425ace7d | 22-Jul-2019 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
sgm775: Fix build fail for TSP support on sgm775
Fixed the path to a source file specified in tsp makefile
Created a platform specific tsp makefile
Change-Id: I89565127c67eff510e48e21fd450af4c3088c
sgm775: Fix build fail for TSP support on sgm775
Fixed the path to a source file specified in tsp makefile
Created a platform specific tsp makefile
Change-Id: I89565127c67eff510e48e21fd450af4c3088c2d4
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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|
| 36ec2bb0 | 14-May-2019 |
Gilad Ben-Yossef <gilad.benyossef@arm.com> |
cryptocell: move Cryptocell specific API into driver
Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driv
cryptocell: move Cryptocell specific API into driver
Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driver code, creating two problems:
- Any none arm board that uses Cryptocell wuld need to
copy and paste the same code.
- Inability to cleanly support multiple versions of Cryptocell
API and products.
Move over Cryptocell specific API calls into the Cryptocell
driver, creating abstraction API where needed.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I9e03ddce90fcc47cfdc747098bece86dbd11c58e
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|
| 6ef6157e | 23-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "n1sdp: fix DMC ECC enablement sequence in N1SDP platform" into integration |
| 4dc74ca3 | 23-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "arm: Shorten the Firmware Update (FWU) process" into integration |
| 7428bbf4 | 22-Jul-2019 |
Manoj Kumar <manoj.kumar3@arm.com> |
n1sdp: fix DMC ECC enablement sequence in N1SDP platform
The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.
This pa
n1sdp: fix DMC ECC enablement sequence in N1SDP platform
The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.
This patch fixes the sequence so that DMCs are set to CONFIG
state before writing to ERR0CTLR0 register and moved back to
READY state after writing.
Change-Id: I1252f3ae0991603bb29234029cddb5fbf869c1b2
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
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|
| 37b70031 | 04-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
arm: Shorten the Firmware Update (FWU) process
The watchdog is configured with a default value of 256 seconds in order
to implement the Trusted Board Boot Requirements.
For the FVP and Juno platfor
arm: Shorten the Firmware Update (FWU) process
The watchdog is configured with a default value of 256 seconds in order
to implement the Trusted Board Boot Requirements.
For the FVP and Juno platforms, the FWU process relies on a watchdog
reset. In order to automate the test of FWU, the length of this process
needs to be as short as possible. Instead of waiting for those 4 minutes
to have a reset by the watchdog, tell it to reset immediately.
There are no side effects as the value of the watchdog's load register
resets to 0xFFFFFFFF.
Tested on Juno.
Change-Id: Ib1aea80ceddc18ff1e0813a5b98dd141ba8a3ff2
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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|
| 53f3751b | 23-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Cortex_hercules: Introduce preliminary cpu support" into integration |
| 294f9ef9 | 14-May-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Cortex_hercules: Introduce preliminary cpu support
Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
| 00c7d5ac | 18-Jun-2019 |
Usama Arif <usama.arif@arm.com> |
plat/arm: Introduce A5 DesignStart platform.
This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.
Currently with
plat/arm: Introduce A5 DesignStart platform.
This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.
Currently with this patch only the primary CPU is booted
and the rest of them wait for an interrupt.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab
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|
| f363deb6 | 03-Jul-2019 |
Balint Dobszay <balint.dobszay@arm.com> |
Rename Cortex-Deimos to Cortex-A77
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> |
| 39c92b62 | 28-Jun-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge changes from topic "av/console-port" into integration
* changes:
qemu: use new console interface in aarch32
warp7: remove old console from makefile
Remove MULTI_CONSOLE_API flag and refe
Merge changes from topic "av/console-port" into integration
* changes:
qemu: use new console interface in aarch32
warp7: remove old console from makefile
Remove MULTI_CONSOLE_API flag and references to it
Console: removed legacy console API
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|
| 5b6ebeec | 04-Apr-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Remove MULTI_CONSOLE_API flag and references to it
The new API becomes the default one.
Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.co
Remove MULTI_CONSOLE_API flag and references to it
The new API becomes the default one.
Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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|
| de8bc83e | 21-Jun-2019 |
Manoj Kumar <manoj.kumar3@arm.com> |
n1sdp: add code for DDR ECC enablement and BL33 copy to DDR
N1SDP platform supports RDIMMs with ECC capability. To use the ECC
capability, the entire DDR memory space has to be zeroed out before
ena
n1sdp: add code for DDR ECC enablement and BL33 copy to DDR
N1SDP platform supports RDIMMs with ECC capability. To use the ECC
capability, the entire DDR memory space has to be zeroed out before
enabling the ECC bits in DMC620. Zeroing out several gigabytes of
memory from SCP is quite time consuming so functions are added that
zeros out the DDR memory from application processor which is
much faster compared to SCP. BL33 binary cannot be copied to DDR memory
before enabling ECC so this is also done by TF-A from IOFPGA-DDR3
memory to main DDR4 memory after ECC is enabled.
Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which
the entire DDR space cannot be accessed as DRAM2 starts in base
0x8080000000. So these macros are redefined for all ARM platforms.
Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
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|