1 /* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 /* Required platform porting definitions */ 20 #define PLATFORM_CORE_COUNT \ 21 (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) 22 23 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 24 PLATFORM_CORE_COUNT) + 1 25 26 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 27 28 /* 29 * Other platform porting definitions are provided by included headers 30 */ 31 32 /* 33 * Required ARM standard platform porting definitions 34 */ 35 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 36 37 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 38 39 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 40 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 41 42 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 43 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 44 45 /* virtual address used by dynamic mem_protect for chunk_base */ 46 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 47 48 /* No SCP in FVP */ 49 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 50 51 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 52 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 53 54 /* 55 * Load address of BL33 for this platform port 56 */ 57 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 58 59 /* 60 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 61 * plat_arm_mmap array defined for each BL stage. 62 */ 63 #if defined(IMAGE_BL31) 64 # if ENABLE_SPM 65 # define PLAT_ARM_MMAP_ENTRIES 9 66 # define MAX_XLAT_TABLES 9 67 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 68 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 69 # else 70 # define PLAT_ARM_MMAP_ENTRIES 8 71 # if USE_DEBUGFS 72 # define MAX_XLAT_TABLES 6 73 # else 74 # define MAX_XLAT_TABLES 5 75 # endif 76 # endif 77 #elif defined(IMAGE_BL32) 78 # define PLAT_ARM_MMAP_ENTRIES 8 79 # define MAX_XLAT_TABLES 5 80 #elif !USE_ROMLIB 81 # define PLAT_ARM_MMAP_ENTRIES 11 82 # define MAX_XLAT_TABLES 5 83 #else 84 # define PLAT_ARM_MMAP_ENTRIES 12 85 # define MAX_XLAT_TABLES 6 86 #endif 87 88 /* 89 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 90 * plus a little space for growth. 91 */ 92 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 93 94 /* 95 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 96 */ 97 98 #if USE_ROMLIB 99 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 100 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 101 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000) 102 #else 103 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 104 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 105 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 106 #endif 107 108 /* 109 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 110 * little space for growth. 111 */ 112 #if TRUSTED_BOARD_BOOT 113 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) 114 #else 115 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION) 116 #endif 117 118 /* 119 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 120 * calculated using the current BL31 PROGBITS debug size plus the sizes of 121 * BL2 and BL1-RW 122 */ 123 #if ENABLE_SPM && !SPM_MM 124 #define PLAT_ARM_MAX_BL31_SIZE UL(0x60000) 125 #else 126 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) 127 #endif 128 129 #ifndef __aarch64__ 130 /* 131 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 132 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 133 * BL2 and BL1-RW 134 */ 135 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 136 #endif 137 138 /* 139 * Size of cacheable stacks 140 */ 141 #if defined(IMAGE_BL1) 142 # if TRUSTED_BOARD_BOOT 143 # define PLATFORM_STACK_SIZE UL(0x1000) 144 # else 145 # define PLATFORM_STACK_SIZE UL(0x440) 146 # endif 147 #elif defined(IMAGE_BL2) 148 # if TRUSTED_BOARD_BOOT 149 # define PLATFORM_STACK_SIZE UL(0x1000) 150 # else 151 # define PLATFORM_STACK_SIZE UL(0x400) 152 # endif 153 #elif defined(IMAGE_BL2U) 154 # define PLATFORM_STACK_SIZE UL(0x400) 155 #elif defined(IMAGE_BL31) 156 # define PLATFORM_STACK_SIZE UL(0x800) 157 #elif defined(IMAGE_BL32) 158 # define PLATFORM_STACK_SIZE UL(0x440) 159 #endif 160 161 #define MAX_IO_DEVICES 3 162 #define MAX_IO_HANDLES 4 163 164 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 165 #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE 166 #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 167 168 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 169 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 170 171 /* 172 * PL011 related constants 173 */ 174 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 175 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 176 177 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 178 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 179 180 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 181 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 182 183 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 184 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 185 186 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 187 188 /* CCI related constants */ 189 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 190 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 191 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 192 193 /* CCI-500/CCI-550 on Base platform */ 194 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 195 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 196 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 197 198 /* CCN related constants. Only CCN 502 is currently supported */ 199 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 200 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 201 202 /* System timer related constants */ 203 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 204 205 /* Mailbox base address */ 206 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 207 208 209 /* TrustZone controller related constants 210 * 211 * Currently only filters 0 and 2 are connected on Base FVP. 212 * Filter 0 : CPU clusters (no access to DRAM by default) 213 * Filter 1 : not connected 214 * Filter 2 : LCDs (access to VRAM allowed by default) 215 * Filter 3 : not connected 216 * Programming unconnected filters will have no effect at the 217 * moment. These filter could, however, be connected in future. 218 * So care should be taken not to configure the unused filters. 219 * 220 * Allow only non-secure access to all DRAM to supported devices. 221 * Give access to the CPUs and Virtio. Some devices 222 * would normally use the default ID so allow that too. 223 */ 224 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 225 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 226 227 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 228 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 229 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 230 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 231 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 232 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 233 234 /* 235 * GIC related constants to cater for both GICv2 and GICv3 instances of an 236 * FVP. They could be overriden at runtime in case the FVP implements the legacy 237 * VE memory map. 238 */ 239 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 240 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 241 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 242 243 /* 244 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 245 * terminology. On a GICv2 system or mode, the lists will be merged and treated 246 * as Group 0 interrupts. 247 */ 248 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 249 ARM_G1S_IRQ_PROPS(grp), \ 250 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 251 GIC_INTR_CFG_LEVEL), \ 252 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 253 GIC_INTR_CFG_LEVEL) 254 255 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 256 257 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 258 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 259 260 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 261 PLAT_SP_IMAGE_NS_BUF_SIZE) 262 263 #define PLAT_SP_PRI PLAT_RAS_PRI 264 265 /* 266 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 267 */ 268 #ifdef __aarch64__ 269 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 270 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 271 #else 272 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 273 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 274 #endif 275 276 #endif /* PLATFORM_DEF_H */ 277