1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef N1SDP_DEF_H 8 #define N1SDP_DEF_H 9 10 /* Non-secure SRAM MMU mapping */ 11 #define N1SDP_NS_SRAM_BASE (0x06000000) 12 #define N1SDP_NS_SRAM_SIZE (0x00010000) 13 #define N1SDP_MAP_NS_SRAM MAP_REGION_FLAT( \ 14 N1SDP_NS_SRAM_BASE, \ 15 N1SDP_NS_SRAM_SIZE, \ 16 MT_DEVICE | MT_RW | MT_SECURE) 17 18 /* SDS Platform information defines */ 19 #define N1SDP_SDS_PLATFORM_INFO_STRUCT_ID 8 20 #define N1SDP_SDS_PLATFORM_INFO_OFFSET 0 21 #define N1SDP_SDS_PLATFORM_INFO_SIZE 4 22 #define N1SDP_MAX_DDR_CAPACITY_GB 64 23 #define N1SDP_MAX_SLAVE_COUNT 16 24 25 /* SDS BL33 image information defines */ 26 #define N1SDP_SDS_BL33_INFO_STRUCT_ID 9 27 #define N1SDP_SDS_BL33_INFO_OFFSET 0 28 #define N1SDP_SDS_BL33_INFO_SIZE 12 29 30 /* DMC memory command registers */ 31 #define N1SDP_DMC0_MEMC_CMD_REG 0x4E000008 32 #define N1SDP_DMC1_MEMC_CMD_REG 0x4E100008 33 34 /* DMC ERR0CTLR0 registers */ 35 #define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708 36 #define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708 37 38 /* DMC memory commands */ 39 #define N1SDP_DMC_MEMC_CMD_CONFIG 0 40 #define N1SDP_DMC_MEMC_CMD_READY 3 41 42 /* DMC ECC enable bit in ERR0CTLR0 register */ 43 #define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1 44 45 /* Base address of non-secure SRAM where Platform information will be filled */ 46 #define N1SDP_PLATFORM_INFO_BASE 0x06008000 47 48 #endif /* N1SDP_DEF_H */ 49