1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <drivers/arm/cci.h> 11 #include <drivers/arm/ccn.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/arm/sp804_delay_timer.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/arm/common/arm_config.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 #include <services/secure_partition.h> 22 23 #include "fvp_private.h" 24 25 /* Defines for GIC Driver build time selection */ 26 #define FVP_GICV2 1 27 #define FVP_GICV3 2 28 29 /******************************************************************************* 30 * arm_config holds the characteristics of the differences between the three FVP 31 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 32 * at each boot stage by the primary before enabling the MMU (to allow 33 * interconnect configuration) & used thereafter. Each BL will have its own copy 34 * to allow independent operation. 35 ******************************************************************************/ 36 arm_config_t arm_config; 37 38 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 39 DEVICE0_SIZE, \ 40 MT_DEVICE | MT_RW | MT_SECURE) 41 42 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 43 DEVICE1_SIZE, \ 44 MT_DEVICE | MT_RW | MT_SECURE) 45 46 /* 47 * Need to be mapped with write permissions in order to set a new non-volatile 48 * counter value. 49 */ 50 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 51 DEVICE2_SIZE, \ 52 MT_DEVICE | MT_RW | MT_SECURE) 53 54 /* 55 * Table of memory regions for various BL stages to map using the MMU. 56 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 57 * of mapping it. 58 * 59 * The flash needs to be mapped as writable in order to erase the FIP's Table of 60 * Contents in case of unrecoverable error (see plat_error_handler()). 61 */ 62 #ifdef IMAGE_BL1 63 const mmap_region_t plat_arm_mmap[] = { 64 ARM_MAP_SHARED_RAM, 65 V2M_MAP_FLASH0_RW, 66 V2M_MAP_IOFPGA, 67 MAP_DEVICE0, 68 MAP_DEVICE1, 69 #if TRUSTED_BOARD_BOOT 70 /* To access the Root of Trust Public Key registers. */ 71 MAP_DEVICE2, 72 /* Map DRAM to authenticate NS_BL2U image. */ 73 ARM_MAP_NS_DRAM1, 74 #endif 75 {0} 76 }; 77 #endif 78 #ifdef IMAGE_BL2 79 const mmap_region_t plat_arm_mmap[] = { 80 ARM_MAP_SHARED_RAM, 81 V2M_MAP_FLASH0_RW, 82 V2M_MAP_IOFPGA, 83 MAP_DEVICE0, 84 MAP_DEVICE1, 85 ARM_MAP_NS_DRAM1, 86 #ifdef __aarch64__ 87 ARM_MAP_DRAM2, 88 #endif 89 #ifdef SPD_tspd 90 ARM_MAP_TSP_SEC_MEM, 91 #endif 92 #if TRUSTED_BOARD_BOOT 93 /* To access the Root of Trust Public Key registers. */ 94 MAP_DEVICE2, 95 #if !BL2_AT_EL3 96 ARM_MAP_BL1_RW, 97 #endif 98 #endif /* TRUSTED_BOARD_BOOT */ 99 #if ENABLE_SPM && SPM_MM 100 ARM_SP_IMAGE_MMAP, 101 #endif 102 #if ENABLE_SPM && !SPM_MM 103 PLAT_MAP_SP_PACKAGE_MEM_RW, 104 #endif 105 #if ARM_BL31_IN_DRAM 106 ARM_MAP_BL31_SEC_DRAM, 107 #endif 108 #ifdef SPD_opteed 109 ARM_MAP_OPTEE_CORE_MEM, 110 ARM_OPTEE_PAGEABLE_LOAD_MEM, 111 #endif 112 {0} 113 }; 114 #endif 115 #ifdef IMAGE_BL2U 116 const mmap_region_t plat_arm_mmap[] = { 117 MAP_DEVICE0, 118 V2M_MAP_IOFPGA, 119 {0} 120 }; 121 #endif 122 #ifdef IMAGE_BL31 123 const mmap_region_t plat_arm_mmap[] = { 124 ARM_MAP_SHARED_RAM, 125 #if USE_DEBUGFS 126 /* Required by devfip, can be removed if devfip is not used */ 127 V2M_MAP_FLASH0_RW, 128 #endif /* USE_DEBUGFS */ 129 ARM_MAP_EL3_TZC_DRAM, 130 V2M_MAP_IOFPGA, 131 MAP_DEVICE0, 132 MAP_DEVICE1, 133 ARM_V2M_MAP_MEM_PROTECT, 134 #if ENABLE_SPM && SPM_MM 135 ARM_SPM_BUF_EL3_MMAP, 136 #endif 137 #if ENABLE_SPM && !SPM_MM 138 PLAT_MAP_SP_PACKAGE_MEM_RO, 139 #endif 140 {0} 141 }; 142 143 #if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM 144 const mmap_region_t plat_arm_secure_partition_mmap[] = { 145 V2M_MAP_IOFPGA_EL0, /* for the UART */ 146 MAP_REGION_FLAT(DEVICE0_BASE, \ 147 DEVICE0_SIZE, \ 148 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 149 ARM_SP_IMAGE_MMAP, 150 ARM_SP_IMAGE_NS_BUF_MMAP, 151 ARM_SP_IMAGE_RW_MMAP, 152 ARM_SPM_BUF_EL0_MMAP, 153 {0} 154 }; 155 #endif 156 #endif 157 #ifdef IMAGE_BL32 158 const mmap_region_t plat_arm_mmap[] = { 159 #ifndef __aarch64__ 160 ARM_MAP_SHARED_RAM, 161 ARM_V2M_MAP_MEM_PROTECT, 162 #endif 163 V2M_MAP_IOFPGA, 164 MAP_DEVICE0, 165 MAP_DEVICE1, 166 {0} 167 }; 168 #endif 169 170 ARM_CASSERT_MMAP 171 172 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 173 static const int fvp_cci400_map[] = { 174 PLAT_FVP_CCI400_CLUS0_SL_PORT, 175 PLAT_FVP_CCI400_CLUS1_SL_PORT, 176 }; 177 178 static const int fvp_cci5xx_map[] = { 179 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 180 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 181 }; 182 183 static unsigned int get_interconnect_master(void) 184 { 185 unsigned int master; 186 u_register_t mpidr; 187 188 mpidr = read_mpidr_el1(); 189 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 190 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 191 192 assert(master < FVP_CLUSTER_COUNT); 193 return master; 194 } 195 #endif 196 197 #if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM 198 /* 199 * Boot information passed to a secure partition during initialisation. Linear 200 * indices in MP information will be filled at runtime. 201 */ 202 static secure_partition_mp_info_t sp_mp_info[] = { 203 [0] = {0x80000000, 0}, 204 [1] = {0x80000001, 0}, 205 [2] = {0x80000002, 0}, 206 [3] = {0x80000003, 0}, 207 [4] = {0x80000100, 0}, 208 [5] = {0x80000101, 0}, 209 [6] = {0x80000102, 0}, 210 [7] = {0x80000103, 0}, 211 }; 212 213 const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { 214 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 215 .h.version = VERSION_1, 216 .h.size = sizeof(secure_partition_boot_info_t), 217 .h.attr = 0, 218 .sp_mem_base = ARM_SP_IMAGE_BASE, 219 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 220 .sp_image_base = ARM_SP_IMAGE_BASE, 221 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 222 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 223 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 224 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 225 .sp_image_size = ARM_SP_IMAGE_SIZE, 226 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 227 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 228 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 229 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 230 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 231 .num_cpus = PLATFORM_CORE_COUNT, 232 .mp_info = &sp_mp_info[0], 233 }; 234 235 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 236 { 237 return plat_arm_secure_partition_mmap; 238 } 239 240 const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( 241 void *cookie) 242 { 243 return &plat_arm_secure_partition_boot_info; 244 } 245 #endif 246 247 /******************************************************************************* 248 * A single boot loader stack is expected to work on both the Foundation FVP 249 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 250 * SYS_ID register provides a mechanism for detecting the differences between 251 * these platforms. This information is stored in a per-BL array to allow the 252 * code to take the correct path.Per BL platform configuration. 253 ******************************************************************************/ 254 void __init fvp_config_setup(void) 255 { 256 unsigned int rev, hbi, bld, arch, sys_id; 257 258 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 259 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 260 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 261 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 262 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 263 264 if (arch != ARCH_MODEL) { 265 ERROR("This firmware is for FVP models\n"); 266 panic(); 267 } 268 269 /* 270 * The build field in the SYS_ID tells which variant of the GIC 271 * memory is implemented by the model. 272 */ 273 switch (bld) { 274 case BLD_GIC_VE_MMAP: 275 ERROR("Legacy Versatile Express memory map for GIC peripheral" 276 " is not supported\n"); 277 panic(); 278 break; 279 case BLD_GIC_A53A57_MMAP: 280 break; 281 default: 282 ERROR("Unsupported board build %x\n", bld); 283 panic(); 284 } 285 286 /* 287 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 288 * for the Foundation FVP. 289 */ 290 switch (hbi) { 291 case HBI_FOUNDATION_FVP: 292 arm_config.flags = 0; 293 294 /* 295 * Check for supported revisions of Foundation FVP 296 * Allow future revisions to run but emit warning diagnostic 297 */ 298 switch (rev) { 299 case REV_FOUNDATION_FVP_V2_0: 300 case REV_FOUNDATION_FVP_V2_1: 301 case REV_FOUNDATION_FVP_v9_1: 302 case REV_FOUNDATION_FVP_v9_6: 303 break; 304 default: 305 WARN("Unrecognized Foundation FVP revision %x\n", rev); 306 break; 307 } 308 break; 309 case HBI_BASE_FVP: 310 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 311 312 /* 313 * Check for supported revisions 314 * Allow future revisions to run but emit warning diagnostic 315 */ 316 switch (rev) { 317 case REV_BASE_FVP_V0: 318 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 319 break; 320 case REV_BASE_FVP_REVC: 321 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 322 ARM_CONFIG_FVP_HAS_CCI5XX); 323 break; 324 default: 325 WARN("Unrecognized Base FVP revision %x\n", rev); 326 break; 327 } 328 break; 329 default: 330 ERROR("Unsupported board HBI number 0x%x\n", hbi); 331 panic(); 332 } 333 334 /* 335 * We assume that the presence of MT bit, and therefore shifted 336 * affinities, is uniform across the platform: either all CPUs, or no 337 * CPUs implement it. 338 */ 339 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 340 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 341 } 342 343 344 void __init fvp_interconnect_init(void) 345 { 346 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 347 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 348 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 349 panic(); 350 } 351 352 plat_arm_interconnect_init(); 353 #else 354 uintptr_t cci_base = 0U; 355 const int *cci_map = NULL; 356 unsigned int map_size = 0U; 357 358 /* Initialize the right interconnect */ 359 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 360 cci_base = PLAT_FVP_CCI5XX_BASE; 361 cci_map = fvp_cci5xx_map; 362 map_size = ARRAY_SIZE(fvp_cci5xx_map); 363 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 364 cci_base = PLAT_FVP_CCI400_BASE; 365 cci_map = fvp_cci400_map; 366 map_size = ARRAY_SIZE(fvp_cci400_map); 367 } else { 368 return; 369 } 370 371 assert(cci_base != 0U); 372 assert(cci_map != NULL); 373 cci_init(cci_base, cci_map, map_size); 374 #endif 375 } 376 377 void fvp_interconnect_enable(void) 378 { 379 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 380 plat_arm_interconnect_enter_coherency(); 381 #else 382 unsigned int master; 383 384 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 385 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 386 master = get_interconnect_master(); 387 cci_enable_snoop_dvm_reqs(master); 388 } 389 #endif 390 } 391 392 void fvp_interconnect_disable(void) 393 { 394 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 395 plat_arm_interconnect_exit_coherency(); 396 #else 397 unsigned int master; 398 399 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 400 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 401 master = get_interconnect_master(); 402 cci_disable_snoop_dvm_reqs(master); 403 } 404 #endif 405 } 406 407 #if TRUSTED_BOARD_BOOT 408 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 409 { 410 assert(heap_addr != NULL); 411 assert(heap_size != NULL); 412 413 return arm_get_mbedtls_heap(heap_addr, heap_size); 414 } 415 #endif 416 417 void fvp_timer_init(void) 418 { 419 #if FVP_USE_SP804_TIMER 420 /* Enable the clock override for SP804 timer 0, which means that no 421 * clock dividers are applied and the raw (35MHz) clock will be used. 422 */ 423 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 424 425 /* Initialize delay timer driver using SP804 dual timer 0 */ 426 sp804_timer_init(V2M_SP804_TIMER0_BASE, 427 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 428 #else 429 generic_delay_timer_init(); 430 431 /* Enable System level generic timer */ 432 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 433 CNTCR_FCREQ(0U) | CNTCR_EN); 434 #endif /* FVP_USE_SP804_TIMER */ 435 } 436