1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <drivers/arm/css/css_mhu_doorbell.h> 10 #include <drivers/arm/css/scmi.h> 11 #include <drivers/arm/css/sds.h> 12 #include <common/debug.h> 13 #include <lib/mmio.h> 14 #include <lib/utils.h> 15 #include <plat/arm/common/plat_arm.h> 16 17 #include "n1sdp_def.h" 18 19 /* 20 * Platform information structure stored in SDS. 21 * This structure holds information about platform's DDR 22 * size which will be used to zero out the memory before 23 * enabling the ECC capability as well as information 24 * about multichip setup 25 * - multichip mode 26 * - slave_count 27 * - Local DDR size in GB, DDR memory in master board 28 * - Remote DDR size in GB, DDR memory in slave board 29 */ 30 struct n1sdp_plat_info { 31 bool multichip_mode; 32 uint8_t slave_count; 33 uint8_t local_ddr_size; 34 uint8_t remote_ddr_size; 35 } __packed; 36 37 /* 38 * BL33 image information structure stored in SDS. 39 * This structure holds the source & destination addresses and 40 * the size of the BL33 image which will be loaded by BL31. 41 */ 42 struct n1sdp_bl33_info { 43 uint32_t bl33_src_addr; 44 uint32_t bl33_dst_addr; 45 uint32_t bl33_size; 46 }; 47 48 static scmi_channel_plat_info_t n1sdp_scmi_plat_info = { 49 .scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE, 50 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, 51 .db_preserve_mask = 0xfffffffe, 52 .db_modify_mask = 0x1, 53 .ring_doorbell = &mhu_ring_doorbell 54 }; 55 56 scmi_channel_plat_info_t *plat_css_get_scmi_info() 57 { 58 return &n1sdp_scmi_plat_info; 59 } 60 61 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 62 { 63 return css_scmi_override_pm_ops(ops); 64 } 65 66 /* 67 * N1SDP platform supports RDIMMs with ECC capability. To use the ECC 68 * capability, the entire DDR memory space has to be zeroed out before 69 * enabling the ECC bits in DMC620. Zeroing out several gigabytes of 70 * memory from SCP is quite time consuming so the following function 71 * is added to zero out the DDR memory from application processor which is 72 * much faster compared to SCP. BL33 binary cannot be copied to DDR memory 73 * before enabling ECC so copy_bl33 function is added to copy BL33 binary 74 * from IOFPGA-DDR3 memory to main DDR4 memory. 75 */ 76 77 void dmc_ecc_setup(uint32_t ddr_size_gb) 78 { 79 uint64_t dram2_size; 80 81 dram2_size = (ddr_size_gb * 1024UL * 1024UL * 1024UL) - 82 ARM_DRAM1_SIZE; 83 84 INFO("Zeroing DDR memories\n"); 85 zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); 86 flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); 87 zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); 88 flush_dcache_range(ARM_DRAM2_BASE, dram2_size); 89 90 INFO("Enabling ECC on DMCs\n"); 91 /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */ 92 mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG); 93 mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG); 94 95 /* Enable ECC in DMCs */ 96 mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); 97 mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); 98 99 /* Set DMCs to READY state */ 100 mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); 101 mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); 102 } 103 104 void copy_bl33(uint32_t src, uint32_t dst, uint32_t size) 105 { 106 uint32_t i; 107 108 INFO("Copying BL33 to DDR memory\n"); 109 for (i = 0; i < size; i = i + 8) 110 mmio_write_64((dst + i), mmio_read_64(src + i)); 111 112 for (i = 0; i < size; i = i + 8) { 113 if (mmio_read_64(src + i) != mmio_read_64(dst + i)) { 114 ERROR("Copy failed!\n"); 115 panic(); 116 } 117 } 118 } 119 120 void bl31_platform_setup(void) 121 { 122 int ret; 123 struct n1sdp_plat_info plat_info; 124 struct n1sdp_bl33_info bl33_info; 125 126 arm_bl31_platform_setup(); 127 128 ret = sds_init(); 129 if (ret != SDS_OK) { 130 ERROR("SDS initialization failed\n"); 131 panic(); 132 } 133 134 ret = sds_struct_read(N1SDP_SDS_PLATFORM_INFO_STRUCT_ID, 135 N1SDP_SDS_PLATFORM_INFO_OFFSET, 136 &plat_info, 137 N1SDP_SDS_PLATFORM_INFO_SIZE, 138 SDS_ACCESS_MODE_NON_CACHED); 139 if (ret != SDS_OK) { 140 ERROR("Error getting platform info from SDS\n"); 141 panic(); 142 } 143 /* Validate plat_info SDS */ 144 if ((plat_info.local_ddr_size == 0) 145 || (plat_info.local_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) 146 || (plat_info.remote_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) 147 || (plat_info.slave_count > N1SDP_MAX_SLAVE_COUNT)) { 148 ERROR("platform info SDS is corrupted\n"); 149 panic(); 150 } 151 152 dmc_ecc_setup(plat_info.local_ddr_size); 153 154 ret = sds_struct_read(N1SDP_SDS_BL33_INFO_STRUCT_ID, 155 N1SDP_SDS_BL33_INFO_OFFSET, 156 &bl33_info, 157 N1SDP_SDS_BL33_INFO_SIZE, 158 SDS_ACCESS_MODE_NON_CACHED); 159 if (ret != SDS_OK) { 160 ERROR("Error getting BL33 info from SDS\n"); 161 panic(); 162 } 163 copy_bl33(bl33_info.bl33_src_addr, 164 bl33_info.bl33_dst_addr, 165 bl33_info.bl33_size); 166 /* 167 * Pass platform information to BL33. This method is followed as 168 * currently there is no BL1/BL2 involved in boot flow of N1SDP. 169 * When TBBR is implemented for N1SDP, this method should be removed 170 * and platform information should be passed to BL33 using NT_FW_CONFIG 171 * passing mechanism. 172 */ 173 mmio_write_32(N1SDP_PLATFORM_INFO_BASE, *(uint32_t *)&plat_info); 174 } 175