Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for

Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for BL2 separation

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feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONF

feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONFIG_ADDR` with a common macro `ARM_HW_CONFIG_ADDR` for
accessing the device tree blob base address.

For FVP the DT address is set to use `ARM_PRELOADED_DTB_BASE` if
provided, falling back to a default address otherwise.

This provides a consistent mechanism for Arm platforms to define and
override the DTB base address used during kernel handoff. It reduces the
chance of misconfiguration, and simplifies platform integration.

Change-Id: Ib668dbb1de9d42cf41c0b0ee9a316f054891752a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fwu): separate bl2 image from rest of the FIP

Create a separate partition for BL2 image in the GPT.
Modify the makefile to package BL2 image and its certificates
into a different FIP image.

Ch

feat(fwu): separate bl2 image from rest of the FIP

Create a separate partition for BL2 image in the GPT.
Modify the makefile to package BL2 image and its certificates
into a different FIP image.

Change-Id: I950883ea0c393a2a063ad9e51bb963cbac742705
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support" into integration

fix(gpt): fix fill_l1_cont_desc() function

GPT library function fill_l1_cont_desc() writes
contiguous descriptors and is called in a loop
by fill_l1_tbl() which fills out GPI entries in
in a single

fix(gpt): fix fill_l1_cont_desc() function

GPT library function fill_l1_cont_desc() writes
contiguous descriptors and is called in a loop
by fill_l1_tbl() which fills out GPI entries in
in a single L1 table. The loop terminates when
the address of the first granule in range 'first'
exceeds address of the last granule (inclusive)
'last'.
This patch fixes the issue when fill_l1_cont_desc()
was iterating through all matching contiguous block
sizes 512, 32 and 2MB in a loop and filling consecutive
smaller descriptors instead of filling a single one with
a maximum size. This resulted for memory region 0x80000000
of size 1.5GB (3*512MB)to be filled with 2 512MB, 8 32MB and
128 2MB contiguous descriptors instead of 3 512MB descriptors
with build option RME_GPT_MAX_BLOCK=512.
This patch also removes unused definition of ARM_PAS_GPI_ANY
macro in fvp_pas_def.h.

Change-Id: I9fcff512af306a57d17dee0bade74d2f3f79b5e9
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge "feat(cpus): add support for Canyon CPU" into integration

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.

When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.

At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e

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feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
S

feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that i

fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that is only implemented on FVP, that conflicts with it.
This sometimes results in failed builds.

DRTM remediation ends with a platform reset. However, there is currently
an error message printed that this is not supported. In this case, the
correct thing to do is to panic and as such this hook is not needed.

Further, the correct sequence to reset the system is different and is
only fully implemented by psci_system_reset(). This is a portable
implementation supported by a wide variety of platform.

So remove plat_system_reset(). Once DRTM remediation properly supports
resetting, the psci_system_reset() function should be used to achieve
reset correctly and portably.

Change-Id: Ia4e150c51aeec613838464fbb0e1d0542f19ccab
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(fvp): add the GICv5 config

The GICv5 FVP needs a gic_config.yaml file to fully configure the
platform. The device tree that is provided is tied to this configuration
and one does not come in th

feat(fvp): add the GICv5 config

The GICv5 FVP needs a gic_config.yaml file to fully configure the
platform. The device tree that is provided is tied to this configuration
and one does not come in the public package. So add a gic_config.yaml to
have an easy means of fully defining the platform with what we expect.
The provided yaml will also boot Linux.

Change-Id: Ib4994807fe397a86f730bd18b163e55453988b5d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sasc

feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Co-developed-by: Lorenzo Pieralisi <lorenzo.pieralisi2@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore(fvp): remove redundant tsp manifest definitions

They are never consumed as the macros that use them are not used.

Change-Id: Ifcc0e7875f0dd3a842c80e3180119cd8f6818c87
Signed-off-by: Boyan Kar

chore(fvp): remove redundant tsp manifest definitions

They are never consumed as the macros that use them are not used.

Change-Id: Ifcc0e7875f0dd3a842c80e3180119cd8f6818c87
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
ref

Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
refactor(versal-net): use the generic GIC driver

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refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes

refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes all GICR frames are
contiguous. This is the original method.

b) via gicv3_rdistif_probe() - called from platform code and requires
gicr_base == 0. It relaxes the requirement for frames to be
contiguous, like in a multichip configuration, and defers the
discovery to core bringup. This was introduced later.

Configurations possible with option a) are also possible with option b)
with only slightly different behaviour. USE_GIC_DRIVER=3 inherited
option b) from plat_gicv3_base.c and as such option a) is unusable.
However, it is unclear from code how this should be used. Clarify this
by requiring platforms initialise with gic_set_gicr_frames() and
adding relevant comments.

Also rename plat_arm_override_gicr_frames() to gic_set_gicr_frames() as
this is not plat arm specific and a part of the generic GIC driver.

Change-Id: I61d77211f8e65dc54cf9904069b500d26a06b5a5
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(fvp): add firmware update agent uuid in StandaloneMm

To support firmware update feature with StandaloneMm,
add firmware update agent uuid for it.

Currently, firmware update feature with Standa

feat(fvp): add firmware update agent uuid in StandaloneMm

To support firmware update feature with StandaloneMm,
add firmware update agent uuid for it.

Currently, firmware update feature with StandaloneMm is supprted
in SPMC_AT_EL3 only.

Change-Id: I095fb969d22aff36a9f8433a7b731b8023496437
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase PLAT_ARM_SPMC_SIZE for rust-spmc

rust-spmc [0] which is experimental S-EL1 SPMC uses
PLAT_ARM_TRUSTED_DRAM area to run itself as much as
16MB (half of PLAT_ARM_TRUSTED_DRAM).

Ho

feat(fvp): increase PLAT_ARM_SPMC_SIZE for rust-spmc

rust-spmc [0] which is experimental S-EL1 SPMC uses
PLAT_ARM_TRUSTED_DRAM area to run itself as much as
16MB (half of PLAT_ARM_TRUSTED_DRAM).

However since PLAT_ARM_SPMC_SIZE is defined as 2MB,
the memory layout specified in arm_spm_def.h defines wrong value.
(i.e) PLAT_SPM_BUF_BASE, secure crb buffer and etc.

To resolve this increase the PLAT_ARM_SPMC_SIZE to 16MB.

Link: https://git.trustedfirmware.org/rust-spmc/rust-spmc.git [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: Ief207d787dd83e7a8e3c55f39fbc25d964ee8b25

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feat(fvp): add StandaloneMm manifest for rust-spmc

The rust-spmc [0] is the BL32 binary which is
SPMC in S-EL1 (experimental).
This patch adds StandaloneMm manifest file used with rust spmc.

Link:

feat(fvp): add StandaloneMm manifest for rust-spmc

The rust-spmc [0] is the BL32 binary which is
SPMC in S-EL1 (experimental).
This patch adds StandaloneMm manifest file used with rust spmc.

Link: https://git.trustedfirmware.org/rust-spmc/rust-spmc.git [0]
Change-Id: I9e79c001257647d4243a1177fe9796f664788406
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Document

feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Documentation/arm64/booting.rst.

In addition:

- Clean up legacy ARM_LINUX_KERNEL_AS_BL33 handling since
USE_KERNEL_DT_CONVENTION now implies this mode for DT handoff.
- Override args.arg0 for BL33 to point to ARM_PRELOADED_DTB_BASE in
RESET_TO_BL31.
- Skip setting the primary MPID in x0 when using this convention.

Change-Id: Ieea8cfe68104b82038b9311613abf13afe7b48f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): organize fvp_stmm_manifest.dts

To generalize manifest file for StandaloneMm for FVP,
organize this manifest file by separating:

* stmm_common.dtsi
- collection of macros to used by

feat(fvp): organize fvp_stmm_manifest.dts

To generalize manifest file for StandaloneMm for FVP,
organize this manifest file by separating:

* stmm_common.dtsi
- collection of macros to used by {plat_}stmm_*.dts(i) files.

* stmm_dev_region.dtsi
- device region template for StandaloneMm.
- If some environment don't required it, it can be excluded in
by not defining STMM_XXX macro.

* stmm_mem_region.dtsi
- memory region template for StandaloneMm.

* stmm_template.dts
- StandaloneMm manifest template defining common root node
information.

* fvp_stmm_{xxx}_manifest.dts
- Main StandaloneMm manifest file.
- According to environment, defines proper STMM_XXX value
to define device/memory region.
- device region can be excluded by not defining some STMM_XXX macro.

This is useful to define new StandaloneMm manifest
in different environments.

Change-Id: Ia9668c4994f589b178872d4d7a18a9f28075df74
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): add pseudo CRB area

To support StandaloneMm with fTPM, add pseudo CRB area used by fTPM.

Change-Id: I43fd00dd23b0f4e6dbc8859808633a0c6051c8b6
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.

feat(fvp): add pseudo CRB area

To support StandaloneMm with fTPM, add pseudo CRB area used by fTPM.

Change-Id: I43fd00dd23b0f4e6dbc8859808633a0c6051c8b6
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMA

feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: I4c3cbf6242f2ccf154b93e9497ab9a21a4b67772
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIF

feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIFEST_SIZE with PAGE_SIZE taken
from PLAT_ARM_HW_CONFIG_SIZE by reducing it as amount of
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

2. increase HAND_OFF transfer list size as much as
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

Change-Id: I56be7783ee4d257e33148f1f623a64bc498f1955
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase secure partition's table mapping count

For tpm event log event region passed to SP,
increase table mapping count.

Change-Id: Ie9f899a611b6715ea9a8bd3f532774d3f8f6955e
Signed-off

feat(fvp): increase secure partition's table mapping count

For tpm event log event region passed to SP,
increase table mapping count.

Change-Id: Ie9f899a611b6715ea9a8bd3f532774d3f8f6955e
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase bl2 mmap tables for handoff

With firmware handoff and SPMC_AT_EL3, the BL2 translation tables
need to be one entry longer than they currently are.
Increase the current max length

feat(fvp): increase bl2 mmap tables for handoff

With firmware handoff and SPMC_AT_EL3, the BL2 translation tables
need to be one entry longer than they currently are.
Increase the current max length by this much to allow to
build these two configurations together.

Change-Id: Ifaeee5010143b53ba4f43c45011eaa8a28456bc5
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase xtable for pseudo CRB for SPM_MM

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPM_MM need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLA

feat(fvp): increase xtable for pseudo CRB for SPM_MM

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPM_MM need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: If48e2eb90e3d4319b0588e4467f2bda0fbaf9a64
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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