feat(fvp): add the GICv5 config

The GICv5 FVP needs a gic_config.yaml file to fully configure the
platform. The device tree that is provided is tied to this configuration
and one does not come in th

feat(fvp): add the GICv5 config

The GICv5 FVP needs a gic_config.yaml file to fully configure the
platform. The device tree that is provided is tied to this configuration
and one does not come in the public package. So add a gic_config.yaml to
have an easy means of fully defining the platform with what we expect.
The provided yaml will also boot Linux.

Change-Id: Ib4994807fe397a86f730bd18b163e55453988b5d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sasc

feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Co-developed-by: Lorenzo Pieralisi <lorenzo.pieralisi2@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore(fvp): remove redundant tsp manifest definitions

They are never consumed as the macros that use them are not used.

Change-Id: Ifcc0e7875f0dd3a842c80e3180119cd8f6818c87
Signed-off-by: Boyan Kar

chore(fvp): remove redundant tsp manifest definitions

They are never consumed as the macros that use them are not used.

Change-Id: Ifcc0e7875f0dd3a842c80e3180119cd8f6818c87
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
ref

Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
refactor(versal-net): use the generic GIC driver

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refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes

refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes all GICR frames are
contiguous. This is the original method.

b) via gicv3_rdistif_probe() - called from platform code and requires
gicr_base == 0. It relaxes the requirement for frames to be
contiguous, like in a multichip configuration, and defers the
discovery to core bringup. This was introduced later.

Configurations possible with option a) are also possible with option b)
with only slightly different behaviour. USE_GIC_DRIVER=3 inherited
option b) from plat_gicv3_base.c and as such option a) is unusable.
However, it is unclear from code how this should be used. Clarify this
by requiring platforms initialise with gic_set_gicr_frames() and
adding relevant comments.

Also rename plat_arm_override_gicr_frames() to gic_set_gicr_frames() as
this is not plat arm specific and a part of the generic GIC driver.

Change-Id: I61d77211f8e65dc54cf9904069b500d26a06b5a5
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(fvp): add firmware update agent uuid in StandaloneMm

To support firmware update feature with StandaloneMm,
add firmware update agent uuid for it.

Currently, firmware update feature with Standa

feat(fvp): add firmware update agent uuid in StandaloneMm

To support firmware update feature with StandaloneMm,
add firmware update agent uuid for it.

Currently, firmware update feature with StandaloneMm is supprted
in SPMC_AT_EL3 only.

Change-Id: I095fb969d22aff36a9f8433a7b731b8023496437
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase PLAT_ARM_SPMC_SIZE for rust-spmc

rust-spmc [0] which is experimental S-EL1 SPMC uses
PLAT_ARM_TRUSTED_DRAM area to run itself as much as
16MB (half of PLAT_ARM_TRUSTED_DRAM).

Ho

feat(fvp): increase PLAT_ARM_SPMC_SIZE for rust-spmc

rust-spmc [0] which is experimental S-EL1 SPMC uses
PLAT_ARM_TRUSTED_DRAM area to run itself as much as
16MB (half of PLAT_ARM_TRUSTED_DRAM).

However since PLAT_ARM_SPMC_SIZE is defined as 2MB,
the memory layout specified in arm_spm_def.h defines wrong value.
(i.e) PLAT_SPM_BUF_BASE, secure crb buffer and etc.

To resolve this increase the PLAT_ARM_SPMC_SIZE to 16MB.

Link: https://git.trustedfirmware.org/rust-spmc/rust-spmc.git [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: Ief207d787dd83e7a8e3c55f39fbc25d964ee8b25

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feat(fvp): add StandaloneMm manifest for rust-spmc

The rust-spmc [0] is the BL32 binary which is
SPMC in S-EL1 (experimental).
This patch adds StandaloneMm manifest file used with rust spmc.

Link:

feat(fvp): add StandaloneMm manifest for rust-spmc

The rust-spmc [0] is the BL32 binary which is
SPMC in S-EL1 (experimental).
This patch adds StandaloneMm manifest file used with rust spmc.

Link: https://git.trustedfirmware.org/rust-spmc/rust-spmc.git [0]
Change-Id: I9e79c001257647d4243a1177fe9796f664788406
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Document

feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Documentation/arm64/booting.rst.

In addition:

- Clean up legacy ARM_LINUX_KERNEL_AS_BL33 handling since
USE_KERNEL_DT_CONVENTION now implies this mode for DT handoff.
- Override args.arg0 for BL33 to point to ARM_PRELOADED_DTB_BASE in
RESET_TO_BL31.
- Skip setting the primary MPID in x0 when using this convention.

Change-Id: Ieea8cfe68104b82038b9311613abf13afe7b48f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): organize fvp_stmm_manifest.dts

To generalize manifest file for StandaloneMm for FVP,
organize this manifest file by separating:

* stmm_common.dtsi
- collection of macros to used by

feat(fvp): organize fvp_stmm_manifest.dts

To generalize manifest file for StandaloneMm for FVP,
organize this manifest file by separating:

* stmm_common.dtsi
- collection of macros to used by {plat_}stmm_*.dts(i) files.

* stmm_dev_region.dtsi
- device region template for StandaloneMm.
- If some environment don't required it, it can be excluded in
by not defining STMM_XXX macro.

* stmm_mem_region.dtsi
- memory region template for StandaloneMm.

* stmm_template.dts
- StandaloneMm manifest template defining common root node
information.

* fvp_stmm_{xxx}_manifest.dts
- Main StandaloneMm manifest file.
- According to environment, defines proper STMM_XXX value
to define device/memory region.
- device region can be excluded by not defining some STMM_XXX macro.

This is useful to define new StandaloneMm manifest
in different environments.

Change-Id: Ia9668c4994f589b178872d4d7a18a9f28075df74
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): add pseudo CRB area

To support StandaloneMm with fTPM, add pseudo CRB area used by fTPM.

Change-Id: I43fd00dd23b0f4e6dbc8859808633a0c6051c8b6
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.

feat(fvp): add pseudo CRB area

To support StandaloneMm with fTPM, add pseudo CRB area used by fTPM.

Change-Id: I43fd00dd23b0f4e6dbc8859808633a0c6051c8b6
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMA

feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: I4c3cbf6242f2ccf154b93e9497ab9a21a4b67772
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIF

feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIFEST_SIZE with PAGE_SIZE taken
from PLAT_ARM_HW_CONFIG_SIZE by reducing it as amount of
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

2. increase HAND_OFF transfer list size as much as
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

Change-Id: I56be7783ee4d257e33148f1f623a64bc498f1955
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase secure partition's table mapping count

For tpm event log event region passed to SP,
increase table mapping count.

Change-Id: Ie9f899a611b6715ea9a8bd3f532774d3f8f6955e
Signed-off

feat(fvp): increase secure partition's table mapping count

For tpm event log event region passed to SP,
increase table mapping count.

Change-Id: Ie9f899a611b6715ea9a8bd3f532774d3f8f6955e
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase bl2 mmap tables for handoff

With firmware handoff and SPMC_AT_EL3, the BL2 translation tables
need to be one entry longer than they currently are.
Increase the current max length

feat(fvp): increase bl2 mmap tables for handoff

With firmware handoff and SPMC_AT_EL3, the BL2 translation tables
need to be one entry longer than they currently are.
Increase the current max length by this much to allow to
build these two configurations together.

Change-Id: Ifaeee5010143b53ba4f43c45011eaa8a28456bc5
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase xtable for pseudo CRB for SPM_MM

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPM_MM need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLA

feat(fvp): increase xtable for pseudo CRB for SPM_MM

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPM_MM need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: If48e2eb90e3d4319b0588e4467f2bda0fbaf9a64
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): add extra DRAM configuration for TZC

As number of ARM_TZC_REGIONS_DEF is reduced by moving
PLAT_SP_IMAGE_NS_BUF_BASE into NS_DRAM1 area [0],
in SPM_MM or SPMC_AT_EL3, extra DRAM can be co

feat(fvp): add extra DRAM configuration for TZC

As number of ARM_TZC_REGIONS_DEF is reduced by moving
PLAT_SP_IMAGE_NS_BUF_BASE into NS_DRAM1 area [0],
in SPM_MM or SPMC_AT_EL3, extra DRAM can be configured in TZC.

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I08e01016f0f4c534e08744117f36fb1fbd1b6e04

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feat(fvp): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Lin

feat(fvp): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: Ic784dfcce921182968854a0fc90487754a8f59c8

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feat(fvp): add SoC name support to FVP

This patch adds support in the FVP platform for the SoC name
field in SMCCC_ARCH_SOC_ID. The returned string is formatted as:

"Arm Platform Revision <SoC Re

feat(fvp): add SoC name support to FVP

This patch adds support in the FVP platform for the SoC name
field in SMCCC_ARCH_SOC_ID. The returned string is formatted as:

"Arm Platform Revision <SoC Revision>"

This adheres to the guideline that the SoC name must not expose
information beyond what is already captured in <SoC Version, SoC
Revision>.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I83da745a754c6fc8f9fa27ee8d8024d6692d3409

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feat(psci): make pabandon support generic

Support for aborted powerdowns does not require much dedicated code.
Rather, it is largely a matter of orchestrating things to happen in the
right order.

T

feat(psci): make pabandon support generic

Support for aborted powerdowns does not require much dedicated code.
Rather, it is largely a matter of orchestrating things to happen in the
right order.

The only exception to this are older secure world dispatchers, which
assume that a CPU_SUSPEND call will be terminal and therefore can
clobber context. This was patched over in common code and hidden behind
a flag. This patch moves this to the dispatchers themselves.

Dispatchers that don't register svc_suspend{_finish} are unaffected.
Those that do must save the NS context before clobbering it and
restoring in only in case of a pabandon. Due to this operation being
non-trivial, this patch makes the assumption that these dispatchers will
only be present on hardware that does not support pabandon and therefore
does not add any contexting for them. In case this assumption ever
changes, asserts are added that should alert us of this change.

Change-Id: I94a907515b782b4d2136c0d274246cfe1d567c0e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(build): use a standard rule to run the preprocessor

There are a few, functionally identical, ways to call the preprocessor
on a non-C file, depending on the file. They differ in subtle, not

refactor(build): use a standard rule to run the preprocessor

There are a few, functionally identical, ways to call the preprocessor
on a non-C file, depending on the file. They differ in subtle, not
entirely correct, ways - one is missing a dependency to the makefiles,
another generates its .d inline, and the prints are different. That has
resulted in platforms reimplementing this functionality, making the
build brittle - a change to the overall build system doesn't propagate.
So add a MAKE_PRE macro that will make a rule with all the bells and
whistles to run the preprocessor on an arbitrary file.

This patch converts the arm platforms' cot_descriptors DTS rules. The
files are renamed to fit with the build rule and all extra flags are
dropped. Those flags are only necessary for building BL2 c files, which
will be passed to the output C file. Only the DTS flags are needed for
the preprocessing step, which will be passed automatically.

Change-Id: I3c1cc0ecf93b87d828f868214928c1bc9bcb5758
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MP

feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MPAM3_EL3: Not trapped as they are part of the EL3 context.
SCTLR_EL3: Not trapped since it is overwritten during
powerdown sequence(Included when HW_ASSISTED_COHERENCY=1)

TPIDR_EL3: Excluded due to its use in crash reporting(It is included
when CRASH_REPORTING=0)

Reference:
https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/FGWTE3-EL3--Fine-Grained-Write-Traps-EL3

Change-Id: Idcb32aaac7d65a0b0e5c90571af00e01a4e9edb1
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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Merge "build(handoff)!: switch to LibTL submodule" into integration

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and pl

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and platform integration logic to link with LibTL as a static
library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibTL is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I1fa31f7b730066c27985d968698e553b00b07c38
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): implement platform API for load and auth image

Introduce and implement a stub implementation of
`plat_lfa_load_auth_image()` for the FVP platform. For AEM FVP, no
actual image loading or

feat(fvp): implement platform API for load and auth image

Introduce and implement a stub implementation of
`plat_lfa_load_auth_image()` for the FVP platform. For AEM FVP, no
actual image loading or authentication is required as of now, as
images are assumed to be pre-loaded and authenticated.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I82e51f5d18db6d5b9c61f9081b451619d761abe8

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