1 /* 2 * Copyright 2022-2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLATFORM_DEF_H 7 #define PLATFORM_DEF_H 8 9 #include <lib/utils_def.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 12 #include <imx95_scmi_def.h> 13 14 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 15 #define PLATFORM_LINKER_ARCH aarch64 16 17 #define PLATFORM_STACK_SIZE 0xB00 18 #define CACHE_WRITEBACK_GRANULE 64 19 20 #define PLAT_PRIMARY_CPU U(0x0) 21 #define PLATFORM_MAX_CPU_PER_CLUSTER U(6) 22 #define PLATFORM_CLUSTER_COUNT U(1) 23 #define PLATFORM_CLUSTER0_CORE_COUNT U(6) 24 #define PLATFORM_CORE_COUNT U(6) 25 26 #define IMX_PWR_LVL0 MPIDR_AFFLVL0 27 28 #define PWR_DOMAIN_AT_MAX_LVL U(1) 29 #define PLAT_MAX_PWR_LVL U(2) 30 #define PLAT_MAX_OFF_STATE U(4) 31 #define PLAT_MAX_RET_STATE U(2) 32 33 /* DDR region 256KB */ 34 #define BL31_BASE U(0x8A200000) 35 #define BL31_LIMIT U(0x8A240000) 36 37 /* non-secure uboot base */ 38 /* TODO */ 39 #define PLAT_NS_IMAGE_OFFSET U(0x90200000) 40 #define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) 41 42 /* GICv4 base address */ 43 #define PLAT_GICD_BASE U(0x48000000) 44 #define PLAT_GICR_BASE U(0x48060000) 45 #define PLAT_ARM_GICR_BASE PLAT_GICR_BASE 46 #define PLAT_ARM_GICD_BASE PLAT_GICD_BASE 47 48 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 36) 49 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36) 50 51 #ifdef SPD_trusty 52 #define MAX_XLAT_TABLES 17 53 #define MAX_MMAP_REGIONS 35 54 #else 55 #define MAX_XLAT_TABLES 14 56 #define MAX_MMAP_REGIONS 32 57 #endif 58 59 #define IMX_LPUART_BASE 0x44380000 60 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */ 61 #define IMX_CONSOLE_BAUDRATE 115200 62 63 #define AIPSx_SIZE U(0x800000) 64 #define AIPS1_BASE U(0x44000000) 65 #define AIPS2_BASE U(0x42000000) 66 #define AIPS3_BASE U(0x42800000) 67 #define AIPS4_BASE U(0x49000000) 68 #define MU_SECURE_BASE U(0x44220000) 69 #define GPIO1_BASE U(0x47400000) 70 #define GPIO2_BASE U(0x43810000) 71 #define GPIO3_BASE U(0x43820000) 72 #define GPIO4_BASE U(0x43840000) 73 #define GPIO5_BASE U(0x43850000) 74 #define WDOG3_BASE U(0x42490000) 75 #define WDOG4_BASE U(0x424A0000) 76 77 #define ELE_MU_BASE U(0x47540000) 78 79 #define SMT_BUFFER_BASE U(0x8A246000) 80 #define SMT_BUFFER_SIZE 0x1000 81 82 #define IMX9_SCMI_PAYLOAD_BASE 0x44221000 83 #define IMX9_MU1_BASE 0x44220000 84 #define MU_GCR_OFF 0x114 85 86 /* Used for GIC_WAKER sync between AP and SM. */ 87 #define SM_AP_SEMA_ADDR 0x442213F8 88 89 #define GPIO_NUM U(4) 90 #define PER_NUM U(15) 91 #define WDOG_NUM U(2) 92 93 #define NETC_IREC_PCI_INT_X0 U(304) 94 95 #define COUNTER_FREQUENCY 24000000 96 97 #define TRUSTY_PARAMS_LEN_BYTES (4096 * 2) 98 #define IMX_TRUSTY_STACK_SIZE 0x200 99 #define TRUSTY_SHARED_MEMORY_OBJ_SIZE (12 * 1024) 100 101 /* 102 * Define a list of Group 1 Secure and Group 0 interrupt properties 103 * as per GICv3 terminology. 104 */ 105 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 106 INTR_PROP_DESC(29U, GIC_HIGHEST_SEC_PRIORITY, grp, \ 107 GIC_INTR_CFG_LEVEL) 108 109 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 110 INTR_PROP_DESC(8U, GIC_HIGHEST_SEC_PRIORITY, \ 111 (grp), GIC_INTR_CFG_LEVEL) 112 113 /* memory mapping */ 114 #define AIPS2_MAP MAP_REGION_FLAT(AIPS2_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW) 115 #define GIC_MAP MAP_REGION_FLAT(PLAT_GICD_BASE, 0x200000, MT_DEVICE | MT_RW) 116 #define AIPS1_MAP MAP_REGION_FLAT(AIPS1_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW) 117 #define GPIO2_MAP MAP_REGION_FLAT(GPIO2_BASE, 0x20000, MT_DEVICE | MT_RW) 118 #define GPIO4_MAP MAP_REGION_FLAT(GPIO4_BASE, 0x20000, MT_DEVICE | MT_RW) 119 #define ELE_MAP MAP_REGION_FLAT(ELE_MU_BASE, 0x10000, MT_DEVICE | MT_RW) 120 121 #endif /* PLATFORM_DEF_H */ 122