1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <context.h> 15 #include <drivers/arm/gic.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 #include <lib/el3_runtime/cpu_data.h> 18 #include <lib/el3_runtime/pubsub_events.h> 19 #include <lib/pmf/pmf.h> 20 #include <lib/runtime_instr.h> 21 #include <plat/common/platform.h> 22 23 #include "psci_private.h" 24 25 /******************************************************************************* 26 * This function does generic and platform specific operations after a wake-up 27 * from standby/retention states at multiple power levels. 28 ******************************************************************************/ 29 static void psci_cpu_suspend_to_standby_finish(unsigned int end_pwrlvl, 30 psci_power_state_t *state_info) 31 { 32 /* 33 * Plat. management: Allow the platform to do operations 34 * on waking up from retention. 35 */ 36 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); 37 38 /* This loses its meaning when not suspending, reset so it's correct for OFF */ 39 psci_set_suspend_pwrlvl(PLAT_MAX_PWR_LVL); 40 } 41 42 /******************************************************************************* 43 * This function does generic and platform specific suspend to power down 44 * operations. 45 ******************************************************************************/ 46 static void psci_suspend_to_pwrdown_start(unsigned int idx, 47 unsigned int end_pwrlvl, 48 unsigned int max_off_lvl, 49 const psci_power_state_t *state_info) 50 { 51 PUBLISH_EVENT_ARG(psci_suspend_pwrdown_start, &idx); 52 53 #if PSCI_OS_INIT_MODE 54 #ifdef PLAT_MAX_CPU_SUSPEND_PWR_LVL 55 end_pwrlvl = PLAT_MAX_CPU_SUSPEND_PWR_LVL; 56 #else 57 end_pwrlvl = PLAT_MAX_PWR_LVL; 58 #endif 59 #endif 60 61 /* Save PSCI target power level for the suspend finisher handler */ 62 psci_set_suspend_pwrlvl(end_pwrlvl); 63 64 /* 65 * Flush the target power level as it might be accessed on power up with 66 * Data cache disabled. 67 */ 68 psci_flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); 69 70 /* 71 * Call the cpu suspend handler registered by the Secure Payload 72 * Dispatcher to let it do any book-keeping. If the handler encounters an 73 * error, it's expected to assert within 74 */ 75 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_suspend != NULL)) { 76 psci_spd_pm->svc_suspend(max_off_lvl); 77 } 78 79 #if !HW_ASSISTED_COHERENCY 80 /* 81 * Plat. management: Allow the platform to perform any early 82 * actions required to power down the CPU. This might be useful for 83 * HW_ASSISTED_COHERENCY = 0 platforms that can safely perform these 84 * actions with data caches enabled. 85 */ 86 if (psci_plat_pm_ops->pwr_domain_suspend_pwrdown_early != NULL) { 87 psci_plat_pm_ops->pwr_domain_suspend_pwrdown_early(state_info); 88 } 89 #endif 90 /* 91 * Arch. management. Initiate power down sequence. 92 */ 93 psci_pwrdown_cpu_start(max_off_lvl); 94 } 95 96 /******************************************************************************* 97 * Top level handler which is called when a cpu wants to suspend its execution. 98 * It is assumed that along with suspending the cpu power domain, power domains 99 * at higher levels until the target power level will be suspended as well. It 100 * coordinates with the platform to negotiate the target state for each of 101 * the power domain level till the target power domain level. It then performs 102 * generic, architectural, platform setup and state management required to 103 * suspend that power domain level and power domain levels below it. 104 * e.g. For a cpu that's to be suspended, it could mean programming the 105 * power controller whereas for a cluster that's to be suspended, it will call 106 * the platform specific code which will disable coherency at the interconnect 107 * level if the cpu is the last in the cluster and also the program the power 108 * controller. 109 * 110 * All the required parameter checks are performed at the beginning and after 111 * the state transition has been done, no further error is expected and it is 112 * not possible to undo any of the actions taken beyond that point. 113 ******************************************************************************/ 114 int psci_cpu_suspend_start(unsigned int idx, 115 unsigned int end_pwrlvl, 116 psci_power_state_t *state_info, 117 unsigned int is_power_down_state) 118 { 119 int rc = PSCI_E_SUCCESS; 120 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; 121 unsigned int max_off_lvl = 0; 122 123 /* 124 * This function must only be called on platforms where the 125 * CPU_SUSPEND platform hooks have been implemented. 126 */ 127 assert((psci_plat_pm_ops->pwr_domain_suspend != NULL) && 128 (psci_plat_pm_ops->pwr_domain_suspend_finish != NULL)); 129 130 /* Get the parent nodes */ 131 psci_get_parent_pwr_domain_nodes(idx, end_pwrlvl, parent_nodes); 132 133 /* 134 * This function acquires the lock corresponding to each power 135 * level so that by the time all locks are taken, the system topology 136 * is snapshot and state management can be done safely. 137 */ 138 psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes); 139 140 /* 141 * We check if there are any pending interrupts after the delay 142 * introduced by lock contention to increase the chances of early 143 * detection that a wake-up interrupt has fired. 144 */ 145 if (read_isr_el1() != 0U) { 146 goto suspend_exit; 147 } 148 149 #if PSCI_OS_INIT_MODE 150 if (psci_suspend_mode == OS_INIT) { 151 /* 152 * This function validates the requested state info for 153 * OS-initiated mode. 154 */ 155 rc = psci_validate_state_coordination(idx, end_pwrlvl, state_info); 156 if (rc != PSCI_E_SUCCESS) { 157 goto suspend_exit; 158 } 159 } else { 160 #endif 161 /* 162 * This function is passed the requested state info and 163 * it returns the negotiated state info for each power level upto 164 * the end level specified. 165 */ 166 psci_do_state_coordination(idx, end_pwrlvl, state_info); 167 #if PSCI_OS_INIT_MODE 168 } 169 #endif 170 171 #if PSCI_OS_INIT_MODE 172 if (psci_plat_pm_ops->pwr_domain_validate_suspend != NULL) { 173 rc = psci_plat_pm_ops->pwr_domain_validate_suspend(state_info); 174 if (rc != PSCI_E_SUCCESS) { 175 goto suspend_exit; 176 } 177 } 178 #endif 179 180 /* Update the target state in the power domain nodes */ 181 psci_set_target_local_pwr_states(idx, end_pwrlvl, state_info); 182 183 #if ENABLE_PSCI_STAT 184 /* Update the last cpu for each level till end_pwrlvl */ 185 psci_stats_update_pwr_down(idx, end_pwrlvl, state_info); 186 #endif 187 188 if (is_power_down_state != 0U) { 189 max_off_lvl = psci_find_max_off_lvl(state_info); 190 psci_suspend_to_pwrdown_start(idx, end_pwrlvl, end_pwrlvl, state_info); 191 } 192 193 #if USE_GIC_DRIVER 194 /* turn the GIC off before we hand off to the platform */ 195 gic_cpuif_disable(idx); 196 #endif /* USE_GIC_DRIVER */ 197 198 /* 199 * Plat. management: Allow the platform to perform the 200 * necessary actions to turn off this cpu e.g. set the 201 * platform defined mailbox with the psci entrypoint, 202 * program the power controller etc. 203 */ 204 psci_plat_pm_ops->pwr_domain_suspend(state_info); 205 206 #if ENABLE_PSCI_STAT 207 plat_psci_stat_accounting_start(state_info); 208 #endif 209 210 /* 211 * Release the locks corresponding to each power level in the 212 * reverse order to which they were acquired. 213 */ 214 psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes); 215 216 #if ENABLE_RUNTIME_INSTRUMENTATION 217 /* 218 * Update the timestamp with cache off. We assume this 219 * timestamp can only be read from the current CPU and the 220 * timestamp cache line will be flushed before return to 221 * normal world on wakeup. 222 */ 223 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 224 RT_INSTR_ENTER_HW_LOW_PWR, 225 PMF_NO_CACHE_MAINT); 226 #endif 227 228 if (is_power_down_state != 0U) { 229 if (psci_plat_pm_ops->pwr_domain_pwr_down != NULL) { 230 /* This function may not return */ 231 psci_plat_pm_ops->pwr_domain_pwr_down(state_info); 232 } 233 234 psci_pwrdown_cpu_end_wakeup(max_off_lvl); 235 } else { 236 /* 237 * We will reach here if only retention/standby states have been 238 * requested at multiple power levels. This means that the cpu 239 * context will be preserved. 240 */ 241 wfi(); 242 } 243 244 #if ENABLE_RUNTIME_INSTRUMENTATION 245 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 246 RT_INSTR_EXIT_HW_LOW_PWR, 247 PMF_NO_CACHE_MAINT); 248 #endif 249 250 psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes); 251 /* 252 * Find out which retention states this CPU has exited from until the 253 * 'end_pwrlvl'. The exit retention state could be deeper than the entry 254 * state as a result of state coordination amongst other CPUs post wfi. 255 */ 256 psci_get_target_local_pwr_states(idx, end_pwrlvl, state_info); 257 258 #if ENABLE_PSCI_STAT 259 plat_psci_stat_accounting_stop(state_info); 260 psci_stats_update_pwr_up(idx, end_pwrlvl, state_info); 261 #endif 262 263 /* 264 * Waking up means we've retained all context. Call the finishers to put 265 * the system back to a usable state. 266 */ 267 if (is_power_down_state != 0U) { 268 psci_cpu_suspend_to_powerdown_finish(idx, max_off_lvl, state_info, true); 269 } else { 270 psci_cpu_suspend_to_standby_finish(end_pwrlvl, state_info); 271 } 272 273 #if USE_GIC_DRIVER 274 /* Turn GIC on after platform has had a chance to do state management */ 275 gic_cpuif_enable(idx); 276 #endif /* USE_GIC_DRIVER */ 277 278 /* 279 * Set the requested and target state of this CPU and all the higher 280 * power domain levels for this CPU to run. 281 */ 282 psci_set_pwr_domains_to_run(idx, end_pwrlvl); 283 284 suspend_exit: 285 psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes); 286 287 return rc; 288 } 289 290 /******************************************************************************* 291 * The following functions finish an earlier suspend request. They 292 * are called by the common finisher routine in psci_common.c. The `state_info` 293 * is the psci_power_state from which this CPU has woken up from. 294 ******************************************************************************/ 295 void psci_cpu_suspend_to_powerdown_finish(unsigned int cpu_idx, unsigned int max_off_lvl, const psci_power_state_t *state_info, bool abandon) 296 { 297 unsigned int counter_freq; 298 299 /* Ensure we have been woken up from a suspended state */ 300 assert((psci_get_aff_info_state() == AFF_STATE_ON) && 301 (is_local_state_off( 302 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]) != 0)); 303 304 /* 305 * Plat. management: Perform the platform specific actions 306 * before we change the state of the cpu e.g. enabling the 307 * gic or zeroing the mailbox register. If anything goes 308 * wrong then assert as there is no way to recover from this 309 * situation. 310 */ 311 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); 312 313 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 314 /* Arch. management: Enable the data cache, stack memory maintenance. */ 315 psci_do_pwrup_cache_maintenance(); 316 #endif 317 318 #if USE_GIC_DRIVER 319 /* GIC on after platform has had its say and MMU is on */ 320 gic_cpuif_enable(cpu_idx); 321 #endif /* USE_GIC_DRIVER */ 322 323 if (!abandon) { 324 /* Re-init the cntfrq_el0 register */ 325 counter_freq = plat_get_syscnt_freq2(); 326 write_cntfrq_el0(counter_freq); 327 } 328 329 /* 330 * Call the cpu suspend finish handler registered by the Secure Payload 331 * Dispatcher to let it do any bookeeping. If the handler encounters an 332 * error, it's expected to assert within 333 */ 334 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_suspend_finish != NULL)) { 335 psci_spd_pm->svc_suspend_finish(max_off_lvl, abandon); 336 } 337 338 /* This loses its meaning when not suspending, reset so it's correct for OFF */ 339 psci_set_suspend_pwrlvl(PLAT_MAX_PWR_LVL); 340 341 PUBLISH_EVENT_ARG(psci_suspend_pwrdown_finish, &cpu_idx); 342 } 343