1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic600_multichip.h> 15 #include <drivers/arm/gic_common.h> 16 17 #include <platform_def.h> 18 19 #include "../common/gic_common_private.h" 20 #include "gicv3_private.h" 21 22 uintptr_t gicv3_get_multichip_base(uint32_t spi_id, uintptr_t gicd_base) 23 { 24 #if GICV3_IMPL_GIC600_MULTICHIP 25 if (gic600_multichip_is_initialized()) { 26 return gic600_multichip_gicd_base_for_spi(spi_id); 27 } 28 #endif 29 return gicd_base; 30 } 31 32 /****************************************************************************** 33 * This function marks the core as awake in the re-distributor and 34 * ensures that the interface is active. 35 *****************************************************************************/ 36 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) 37 { 38 uint32_t waker = gicr_read_waker(gicr_base); 39 40 /* Only try to mark it as awake when it is asleep. */ 41 if ((waker & WAKER_PS_BIT) == 0U) { 42 return; 43 } 44 45 /* 46 * ProcessorSleep must only be changed when ChildrenAsleep is 1. 47 * If PS is 1 and CA isn't, wait for that to happen, but warn. 48 */ 49 if ((waker & WAKER_CA_BIT) == 0U) { 50 WARN("GICR_WAKER.ChildrenAsleep unexpectedly set, waiting...\n"); 51 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { 52 } 53 } 54 55 /* Mark the connected core as awake */ 56 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); 57 58 /* Wait till the WAKER_CA_BIT changes to 0 */ 59 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) { 60 } 61 } 62 63 /****************************************************************************** 64 * This function marks the core as asleep in the re-distributor and ensures 65 * that the interface is quiescent. 66 *****************************************************************************/ 67 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) 68 { 69 /* Mark the connected core as asleep */ 70 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); 71 72 /* Wait till the WAKER_CA_BIT changes to 1 */ 73 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { 74 } 75 } 76 77 /******************************************************************************* 78 * This function probes the Redistributor frames when the driver is initialised 79 * and saves their base addresses. These base addresses are used later to 80 * initialise each Redistributor interface. 81 ******************************************************************************/ 82 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 83 unsigned int rdistif_num, 84 uintptr_t gicr_base, 85 mpidr_hash_fn mpidr_to_core_pos) 86 { 87 u_register_t mpidr; 88 unsigned int proc_num; 89 uint64_t typer_val; 90 uintptr_t rdistif_base = gicr_base; 91 92 assert(rdistif_base_addrs != NULL); 93 94 /* 95 * Iterate over the Redistributor frames. Store the base address of each 96 * frame in the platform provided array. Use the "Processor Number" 97 * field to index into the array if the platform has not provided a hash 98 * function to convert an MPIDR (obtained from the "Affinity Value" 99 * field into a linear index. 100 */ 101 do { 102 typer_val = gicr_read_typer(rdistif_base); 103 if (mpidr_to_core_pos != NULL) { 104 mpidr = mpidr_from_gicr_typer(typer_val); 105 proc_num = mpidr_to_core_pos(mpidr); 106 } else { 107 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & 108 TYPER_PROC_NUM_MASK; 109 } 110 111 if (proc_num < rdistif_num) { 112 rdistif_base_addrs[proc_num] = rdistif_base; 113 } 114 rdistif_base += gicv3_redist_size(typer_val); 115 } while ((typer_val & TYPER_LAST_BIT) == 0U); 116 } 117 118 /******************************************************************************* 119 * Helper function to get the maximum SPI INTID + 1. 120 ******************************************************************************/ 121 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base) 122 { 123 unsigned int spi_limit; 124 unsigned int typer_reg = gicd_read_typer(gicd_base); 125 126 /* (maximum SPI INTID + 1) is equal to 32 * (GICD_TYPER.ITLinesNumber+1) */ 127 spi_limit = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 128 129 /* Filter out special INTIDs 1020-1023 */ 130 if (spi_limit > (MAX_SPI_ID + 1U)) { 131 return MAX_SPI_ID + 1U; 132 } 133 134 return spi_limit; 135 } 136 137 #if GIC_EXT_INTID 138 /******************************************************************************* 139 * Helper function to get the maximum ESPI INTID + 1. 140 ******************************************************************************/ 141 unsigned int gicv3_get_espi_limit(uintptr_t gicd_base) 142 { 143 unsigned int typer_reg = gicd_read_typer(gicd_base); 144 145 /* Check if extended SPI range is implemented */ 146 if ((typer_reg & TYPER_ESPI) != 0U) { 147 /* 148 * (maximum ESPI INTID + 1) is equal to 149 * 32 * (GICD_TYPER.ESPI_range + 1) + 4096 150 */ 151 return ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 152 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID; 153 } 154 155 return 0U; 156 } 157 #endif /* GIC_EXT_INTID */ 158 159 /******************************************************************************* 160 * Helper function to configure the default attributes of (E)SPIs. 161 ******************************************************************************/ 162 void gicv3_spis_config_defaults(uintptr_t gicd_base) 163 { 164 unsigned int i, num_ints; 165 #if GIC_EXT_INTID 166 unsigned int num_eints; 167 #endif 168 169 num_ints = gicv3_get_spi_limit(gicd_base); 170 INFO("Maximum SPI INTID supported: %u\n", num_ints - 1); 171 172 /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */ 173 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) { 174 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U); 175 } 176 177 #if GIC_EXT_INTID 178 num_eints = gicv3_get_espi_limit(gicd_base); 179 if (num_eints != 0U) { 180 INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1); 181 182 for (i = MIN_ESPI_ID; i < num_eints; 183 i += (1U << IGROUPR_SHIFT)) { 184 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U); 185 } 186 } else { 187 INFO("ESPI range is not implemented.\n"); 188 } 189 #endif 190 191 /* Setup the default (E)SPI priorities doing four at a time */ 192 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) { 193 gicd_write_ipriorityr(gicv3_get_multichip_base(i, gicd_base), i, GICD_IPRIORITYR_DEF_VAL); 194 } 195 196 #if GIC_EXT_INTID 197 for (i = MIN_ESPI_ID; i < num_eints; 198 i += (1U << IPRIORITYR_SHIFT)) { 199 gicd_write_ipriorityr(gicv3_get_multichip_base(i, gicd_base), i, GICD_IPRIORITYR_DEF_VAL); 200 } 201 #endif 202 /* 203 * Treat all (E)SPIs as level triggered by default, write 16 at a time 204 */ 205 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) { 206 gicd_write_icfgr(gicv3_get_multichip_base(i, gicd_base), i, 0U); 207 } 208 209 #if GIC_EXT_INTID 210 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) { 211 gicd_write_icfgr(gicv3_get_multichip_base(i, gicd_base), i, 0U); 212 } 213 #endif 214 } 215 216 /******************************************************************************* 217 * Helper function to configure properties of secure (E)SPIs 218 ******************************************************************************/ 219 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 220 const interrupt_prop_t *interrupt_props, 221 unsigned int interrupt_props_num) 222 { 223 unsigned int i; 224 const interrupt_prop_t *current_prop; 225 unsigned long long gic_affinity_val; 226 unsigned int ctlr_enable = 0U; 227 228 /* Make sure there's a valid property array */ 229 if (interrupt_props_num > 0U) { 230 assert(interrupt_props != NULL); 231 } 232 233 for (i = 0U; i < interrupt_props_num; i++) { 234 current_prop = &interrupt_props[i]; 235 236 unsigned int intr_num = current_prop->intr_num; 237 uintptr_t multichip_gicd_base; 238 239 /* Skip SGI, (E)PPI and LPI interrupts */ 240 if (!IS_SPI(intr_num)) { 241 continue; 242 } 243 244 multichip_gicd_base = 245 gicv3_get_multichip_base(intr_num, gicd_base); 246 247 /* Configure this interrupt as a secure interrupt */ 248 gicd_clr_igroupr(multichip_gicd_base, intr_num); 249 250 /* Configure this interrupt as G0 or a G1S interrupt */ 251 assert((current_prop->intr_grp == INTR_GROUP0) || 252 (current_prop->intr_grp == INTR_GROUP1S)); 253 254 if (current_prop->intr_grp == INTR_GROUP1S) { 255 gicd_set_igrpmodr(multichip_gicd_base, intr_num); 256 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 257 } else { 258 gicd_clr_igrpmodr(multichip_gicd_base, intr_num); 259 ctlr_enable |= CTLR_ENABLE_G0_BIT; 260 } 261 262 /* Set interrupt configuration */ 263 gicd_set_icfgr(multichip_gicd_base, intr_num, 264 current_prop->intr_cfg); 265 266 /* Set the priority of this interrupt */ 267 gicd_set_ipriorityr(multichip_gicd_base, intr_num, 268 current_prop->intr_pri); 269 270 /* Target (E)SPIs to the primary CPU */ 271 gic_affinity_val = 272 gicd_irouter_val_from_mpidr(read_mpidr(), 0U); 273 gicd_write_irouter(multichip_gicd_base, intr_num, 274 gic_affinity_val); 275 276 /* Enable this interrupt */ 277 gicd_set_isenabler(multichip_gicd_base, intr_num); 278 } 279 280 return ctlr_enable; 281 } 282 283 /******************************************************************************* 284 * Helper function to configure the default attributes of (E)PPIs/SGIs 285 ******************************************************************************/ 286 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) 287 { 288 unsigned int i, ppi_regs_num, regs_num; 289 290 #if GIC_EXT_INTID 291 /* Calculate number of PPI registers */ 292 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 293 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 294 /* All other values except PPInum [0-2] are reserved */ 295 if (ppi_regs_num > 3U) { 296 ppi_regs_num = 1U; 297 } 298 #else 299 ppi_regs_num = 1U; 300 #endif 301 /* 302 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 303 * This is a more scalable approach as it avoids clearing 304 * the enable bits in the GICD_CTLR. 305 */ 306 for (i = 0U; i < ppi_regs_num; ++i) { 307 gicr_write_icenabler(gicr_base, i, ~0U); 308 } 309 310 /* Wait for pending writes to GICR_ICENABLER */ 311 gicr_wait_for_pending_write(gicr_base); 312 313 /* 32 interrupt IDs per GICR_IGROUPR register */ 314 for (i = 0U; i < ppi_regs_num; ++i) { 315 /* Treat all SGIs/(E)PPIs as G1NS by default */ 316 gicr_write_igroupr(gicr_base, i, ~0U); 317 } 318 319 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 320 regs_num = ppi_regs_num << 3; 321 for (i = 0U; i < regs_num; ++i) { 322 /* Setup the default (E)PPI/SGI priorities doing 4 at a time */ 323 gicr_write_ipriorityr(gicr_base, i << 2, GICD_IPRIORITYR_DEF_VAL); 324 } 325 326 /* 16 interrupt IDs per GICR_ICFGR register */ 327 regs_num = ppi_regs_num << 1; 328 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) { 329 /* Configure all (E)PPIs as level triggered by default */ 330 gicr_write_icfgr(gicr_base, i, 0U); 331 } 332 } 333 334 /******************************************************************************* 335 * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs 336 ******************************************************************************/ 337 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 338 const interrupt_prop_t *interrupt_props, 339 unsigned int interrupt_props_num) 340 { 341 unsigned int i; 342 const interrupt_prop_t *current_prop; 343 unsigned int ctlr_enable = 0U; 344 345 /* Make sure there's a valid property array */ 346 if (interrupt_props_num > 0U) { 347 assert(interrupt_props != NULL); 348 } 349 350 for (i = 0U; i < interrupt_props_num; i++) { 351 current_prop = &interrupt_props[i]; 352 353 unsigned int intr_num = current_prop->intr_num; 354 355 /* Skip (E)SPI interrupt */ 356 if (!IS_SGI_PPI(intr_num)) { 357 continue; 358 } 359 360 /* Configure this interrupt as a secure interrupt */ 361 gicr_clr_igroupr(gicr_base, intr_num); 362 363 /* Configure this interrupt as G0 or a G1S interrupt */ 364 assert((current_prop->intr_grp == INTR_GROUP0) || 365 (current_prop->intr_grp == INTR_GROUP1S)); 366 367 if (current_prop->intr_grp == INTR_GROUP1S) { 368 gicr_set_igrpmodr(gicr_base, intr_num); 369 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 370 } else { 371 gicr_clr_igrpmodr(gicr_base, intr_num); 372 ctlr_enable |= CTLR_ENABLE_G0_BIT; 373 } 374 375 /* Set the priority of this interrupt */ 376 gicr_set_ipriorityr(gicr_base, intr_num, 377 current_prop->intr_pri); 378 379 /* 380 * Set interrupt configuration for (E)PPIs. 381 * Configurations for SGIs 0-15 are ignored. 382 */ 383 if (intr_num >= MIN_PPI_ID) { 384 gicr_set_icfgr(gicr_base, intr_num, 385 current_prop->intr_cfg); 386 } 387 388 /* Enable this interrupt */ 389 gicr_set_isenabler(gicr_base, intr_num); 390 } 391 392 return ctlr_enable; 393 } 394 395 /** 396 * gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region 397 * @gicr_frame: base address of the GICR region to check 398 * 399 * This iterates over the GICR_TYPER registers of multiple GICR frames in 400 * a GICR region, to find the instance which has the LAST bit set. For most 401 * systems this corresponds to the number of cores handled by a redistributor, 402 * but there could be disabled cores among them. 403 * It assumes that each GICR region is fully accessible (till the LAST bit 404 * marks the end of the region). 405 * If a platform has multiple GICR regions, this function would need to be 406 * called multiple times, providing the respective GICR base address each time. 407 * 408 * Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT) 409 ******************************************************************************/ 410 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame) 411 { 412 uintptr_t rdistif_base = gicr_frame; 413 unsigned int count; 414 415 for (count = 1U; count < PLATFORM_CORE_COUNT; count++) { 416 uint64_t typer_val = gicr_read_typer(rdistif_base); 417 418 if ((typer_val & TYPER_LAST_BIT) != 0U) { 419 break; 420 } 421 rdistif_base += gicv3_redist_size(typer_val); 422 } 423 424 return count; 425 } 426 427 unsigned int gicv3_get_component_partnum(const uintptr_t gic_frame) 428 { 429 unsigned int part_id; 430 431 /* 432 * The lower 8 bits of PIDR0, complemented by the lower 4 bits of 433 * PIDR1 contain a part number identifying the GIC component at a 434 * particular base address. 435 */ 436 part_id = mmio_read_32(gic_frame + GICD_PIDR0_GICV3) & 0xffU; 437 part_id |= (mmio_read_32(gic_frame + GICD_PIDR1_GICV3) << 8) & 0xf00U; 438 439 return part_id; 440 } 441 442 /******************************************************************************* 443 * Helper function to return product ID and revision of GIC 444 * @gicd_base: base address of the GIC distributor 445 * @gic_prod_id: retrieved product id of GIC 446 * @gic_rev: retrieved revision of GIC 447 ******************************************************************************/ 448 void gicv3_get_component_prodid_rev(const uintptr_t gicd_base, 449 unsigned int *gic_prod_id, 450 uint8_t *gic_rev) 451 { 452 unsigned int gicd_iidr; 453 uint8_t gic_variant; 454 455 gicd_iidr = gicd_read_iidr(gicd_base); 456 *gic_prod_id = gicd_iidr >> IIDR_PRODUCT_ID_SHIFT; 457 *gic_prod_id &= IIDR_PRODUCT_ID_MASK; 458 459 gic_variant = (uint8_t)(gicd_iidr >> IIDR_VARIANT_SHIFT); 460 gic_variant &= IIDR_VARIANT_MASK; 461 462 *gic_rev = (uint8_t)(gicd_iidr >> IIDR_REV_SHIFT); 463 *gic_rev &= IIDR_REV_MASK; 464 465 /* 466 * pack gic variant and gic_rev in 1 byte 467 * gic_rev = gic_variant[7:4] and gic_rev[0:3] 468 */ 469 *gic_rev |= gic_variant << 0x4; 470 471 } 472