1 /* 2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 #include <plat_arm.h> 19 #include <plat_console.h> 20 #include <plat_clkfunc.h> 21 22 #include <plat_fdt.h> 23 #include <plat_private.h> 24 #include <plat_startup.h> 25 #include <pm_api_sys.h> 26 #include <pm_client.h> 27 #include <pm_ipi.h> 28 #include <versal_net_def.h> 29 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 static const uintptr_t gicr_base_addrs[2] = { 34 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */ 35 0U /* Zero Termination */ 36 }; 37 38 /* 39 * Return a pointer to the 'entry_point_info' structure of the next image for 40 * the security state specified. BL33 corresponds to the non-secure image type 41 * while BL32 corresponds to the secure image type. A NULL pointer is returned 42 * if the image does not exist. 43 */ 44 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 45 { 46 assert(sec_state_is_valid(type)); 47 48 if (type == NON_SECURE) { 49 return &bl33_image_ep_info; 50 } 51 52 return &bl32_image_ep_info; 53 } 54 55 /* 56 * Set the build time defaults,if we can't find any config data. 57 */ 58 static inline void bl31_set_default_config(void) 59 { 60 bl32_image_ep_info.pc = BL32_BASE; 61 bl32_image_ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID); 62 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 63 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 64 DISABLE_ALL_EXCEPTIONS); 65 } 66 67 /* Define read and write function for clusterbusqos register */ 68 DEFINE_RENAME_SYSREG_RW_FUNCS(cluster_bus_qos, S3_0_C15_C4_4) 69 70 static void versal_net_setup_qos(void) 71 { 72 int ret; 73 74 ret = read_cluster_bus_qos(); 75 INFO("BL31: default cluster bus qos: 0x%x\n", ret); 76 write_cluster_bus_qos(0); 77 ret = read_cluster_bus_qos(); 78 INFO("BL31: cluster bus qos written: 0x%x\n", ret); 79 } 80 81 /* 82 * Perform any BL31 specific platform actions. Here is an opportunity to copy 83 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 84 * are lost (potentially). This needs to be done before the MMU is initialized 85 * so that the memory layout can be used while creating page tables. 86 */ 87 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 88 u_register_t arg2, u_register_t arg3) 89 { 90 (void)arg0; 91 (void)arg1; 92 (void)arg2; 93 (void)arg3; 94 95 #if !(TFA_NO_PM) 96 uint64_t tfa_handoff_addr, buff[HANDOFF_PARAMS_MAX_SIZE] = {0}; 97 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; 98 enum pm_ret_status ret_status; 99 #if DEBUG 100 uint32_t boot_mode; 101 #endif 102 #endif /* !(TFA_NO_PM) */ 103 104 board_detection(); 105 106 switch (platform_id) { 107 case VERSAL_NET_SPP: 108 cpu_clock = 1000000; 109 break; 110 case VERSAL_NET_EMU: 111 cpu_clock = 3660000; 112 break; 113 case VERSAL_NET_QEMU: 114 /* Random values now */ 115 cpu_clock = 100000000; 116 break; 117 case VERSAL_NET_SILICON: 118 cpu_clock = 100000000; 119 break; 120 default: 121 panic(); 122 } 123 124 syscnt_freq_config_setup(); 125 126 set_cnt_freq(); 127 128 /* Initialize the platform config for future decision making */ 129 versal_net_config_setup(); 130 131 setup_console(); 132 133 NOTICE("TF-A running on %s %d.%d\n", board_name_decode(), 134 platform_version / 10U, platform_version % 10U); 135 136 versal_net_setup_qos(); 137 138 139 /* 140 * Do initial security configuration to allow DRAM/device access. On 141 * Base VERSAL_NET only DRAM security is programmable (via TrustZone), but 142 * other platforms might have more programmable security devices 143 * present. 144 */ 145 146 /* Populate common information for BL32 and BL33 */ 147 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 148 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 149 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 150 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 151 #if !(TFA_NO_PM) 152 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1U, PM_LOAD_GET_HANDOFF_PARAMS, 153 (uintptr_t)buff >> 32U, (uintptr_t)buff, max_size); 154 155 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 156 if (ret_status == PM_RET_SUCCESS) { 157 enum xbl_handoff xbl_ret; 158 159 tfa_handoff_addr = (uintptr_t)&buff; 160 161 xbl_ret = xbl_handover(&bl32_image_ep_info, &bl33_image_ep_info, 162 tfa_handoff_addr); 163 if (xbl_ret == XBL_HANDOFF_SUCCESS) { 164 goto success; 165 } 166 #if DEBUG 167 get_boot_mode(&boot_mode); 168 if ((xbl_ret != XBL_HANDOFF_SUCCESS) && (boot_mode == JTAG_MODE)) { 169 bl31_set_default_config(); 170 goto success; 171 } 172 #endif 173 } else { 174 bl31_set_default_config(); 175 goto success; 176 } 177 178 ERROR("PLM to TF-A handover failed or not in default boot mode\n"); 179 panic(); 180 181 success: 182 INFO("BL31: PLM to TF-A handover success or default config is set\n"); 183 184 #else 185 bl31_set_default_config(); 186 #endif /* !(TFA_NO_PM) */ 187 188 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 189 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 190 } 191 192 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 193 194 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 195 { 196 static uint32_t index; 197 uint32_t i; 198 int32_t ret = 0; 199 200 /* Validate 'handler' and 'id' parameters */ 201 if ((handler == NULL) || (index >= MAX_INTR_EL3)) { 202 ret = -EINVAL; 203 goto exit_label; 204 } 205 206 /* Check if a handler has already been registered */ 207 for (i = 0; i < index; i++) { 208 if (id == type_el3_interrupt_table[i].id) { 209 ret = -EALREADY; 210 goto exit_label; 211 } 212 } 213 214 type_el3_interrupt_table[index].id = id; 215 type_el3_interrupt_table[index].handler = handler; 216 217 index++; 218 219 exit_label: 220 return ret; 221 } 222 223 #if SDEI_SUPPORT 224 static int rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 225 void *handle, void *cookie) 226 #else 227 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 228 void *handle, void *cookie) 229 #endif 230 { 231 uint32_t intr_id; 232 uint32_t i; 233 interrupt_type_handler_t handler = NULL; 234 235 #if SDEI_SUPPORT 236 /* when SDEI_SUPPORT is enabled, ehf_el3_interrupt_handler 237 * reads the interrupt id prior to calling the 238 * rdo_el3_interrupt_handler and passes that id to the 239 * handler. 240 */ 241 intr_id = id; 242 #else 243 intr_id = plat_ic_get_pending_interrupt_id(); 244 #endif 245 246 for (i = 0; i < MAX_INTR_EL3; i++) { 247 if (intr_id == type_el3_interrupt_table[i].id) { 248 handler = type_el3_interrupt_table[i].handler; 249 } 250 } 251 252 if (handler != NULL) { 253 (void)handler(intr_id, flags, handle, cookie); 254 } 255 256 return 0; 257 } 258 259 void bl31_platform_setup(void) 260 { 261 prepare_dtb(); 262 263 gic_set_gicr_frames(gicr_base_addrs); 264 } 265 266 void bl31_plat_runtime_setup(void) 267 { 268 #if !SDEI_SUPPORT 269 uint64_t flags = 0; 270 int32_t rc; 271 272 set_interrupt_rm_flag(flags, NON_SECURE); 273 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 274 rdo_el3_interrupt_handler, flags); 275 if (rc != 0) { 276 panic(); 277 } 278 #else 279 ehf_register_priority_handler(PLAT_IPI_PRI, rdo_el3_interrupt_handler); 280 #endif 281 } 282 283 /* 284 * Perform the very early platform specific architectural setup here. 285 */ 286 void bl31_plat_arch_setup(void) 287 { 288 const mmap_region_t bl_regions[] = { 289 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 290 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 291 MT_MEMORY | MT_RW | MT_NS), 292 #endif 293 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 294 MT_MEMORY | MT_RW | MT_SECURE), 295 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 296 MT_CODE | MT_SECURE), 297 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 298 MT_RO_DATA | MT_SECURE), 299 {0} 300 }; 301 302 setup_page_tables(bl_regions, plat_get_mmap()); 303 enable_mmu(0); 304 } 305