1# Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 2# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 3# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4# 5# SPDX-License-Identifier: BSD-3-Clause 6 7PLAT_PATH := plat/xilinx/versal_net 8 9# A78 Erratum for SoC 10ERRATA_A78_AE_1941500 := 1 11ERRATA_A78_AE_1951502 := 1 12ERRATA_A78_AE_2376748 := 1 13ERRATA_A78_AE_2395408 := 1 14 15override PROGRAMMABLE_RESET_ADDRESS := 1 16PSCI_EXTENDED_STATE_ID := 1 17SEPARATE_CODE_AND_RODATA := 1 18override RESET_TO_BL31 := 1 19PL011_GENERIC_UART := 1 20IPI_CRC_CHECK := 0 21USE_GIC_DRIVER := 3 22GIC_ENABLE_V4_EXTN := 0 23GICV3_SUPPORT_GIC600 := 1 24TFA_NO_PM := 0 25CPU_PWRDWN_SGI ?= 6 26$(eval $(call add_define_val,CPU_PWR_DOWN_REQ_INTR,ARM_IRQ_SEC_SGI_${CPU_PWRDWN_SGI})) 27 28override CTX_INCLUDE_AARCH32_REGS := 0 29 30ifdef TFA_NO_PM 31 $(eval $(call add_define,TFA_NO_PM)) 32endif 33 34ifdef VERSAL_NET_ATF_MEM_BASE 35 $(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE)) 36 37 ifndef VERSAL_NET_ATF_MEM_SIZE 38 $(error "VERSAL_NET_ATF_MEM_BASE defined without VERSAL_NET_ATF_MEM_SIZE") 39 endif 40 $(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE)) 41 42 ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE 43 $(eval $(call add_define,VERSAL_NET_ATF_MEM_PROGBITS_SIZE)) 44 endif 45endif 46 47ifdef VERSAL_NET_BL32_MEM_BASE 48 $(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE)) 49 50 ifndef VERSAL_NET_BL32_MEM_SIZE 51 $(error "VERSAL_NET_BL32_MEM_BASE defined without VERSAL_NET_BL32_MEM_SIZE") 52 endif 53 $(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE)) 54endif 55 56ifdef IPI_CRC_CHECK 57 $(eval $(call add_define,IPI_CRC_CHECK)) 58endif 59 60USE_COHERENT_MEM := 0 61HW_ASSISTED_COHERENCY := 1 62 63VERSAL_NET_CONSOLE ?= pl011 64ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none)) 65else 66 $(error Please define VERSAL_NET_CONSOLE) 67endif 68 69$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE})) 70 71ifdef XILINX_OF_BOARD_DTB_ADDR 72XLNX_DT_CFG := 1 73$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) 74else 75XLNX_DT_CFG := 0 76endif 77$(eval $(call add_define,XLNX_DT_CFG)) 78 79# Runtime console in default console in DEBUG build 80ifeq ($(DEBUG), 1) 81CONSOLE_RUNTIME ?= $(VERSAL_NET_CONSOLE) 82endif 83 84# Runtime console 85ifdef CONSOLE_RUNTIME 86ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb)) 87$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME})) 88else 89$(error "Please define CONSOLE_RUNTIME") 90endif 91endif 92 93# enable assert() for release/debug builds 94ENABLE_ASSERTIONS := 1 95 96PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 97 -Iplat/xilinx/common/include/ \ 98 -Iplat/xilinx/common/ipi_mailbox_service/ \ 99 -I${PLAT_PATH}/include/ \ 100 -Iplat/xilinx/versal/pm_service/ 101 102include lib/xlat_tables_v2/xlat_tables.mk 103include lib/libfdt/libfdt.mk 104 105PLAT_BL_COMMON_SOURCES := \ 106 drivers/arm/dcc/dcc_console.c \ 107 drivers/delay_timer/delay_timer.c \ 108 drivers/delay_timer/generic_delay_timer.c \ 109 drivers/arm/pl011/aarch64/pl011_console.S \ 110 plat/common/aarch64/crash_console_helpers.S \ 111 plat/arm/common/arm_common.c \ 112 ${PLAT_PATH}/aarch64/versal_net_helpers.S \ 113 ${PLAT_PATH}/aarch64/versal_net_common.c \ 114 ${PLAT_PATH}/plat_topology.c \ 115 ${XLAT_TABLES_LIB_SRCS} 116 117BL31_SOURCES += drivers/arm/cci/cci.c \ 118 lib/cpus/aarch64/cortex_a78_ae.S \ 119 lib/cpus/aarch64/cortex_a78.S \ 120 plat/common/plat_psci_common.c 121ifeq ($(TFA_NO_PM), 0) 122BL31_SOURCES += plat/xilinx/common/pm_service/pm_api_sys.c \ 123 plat/xilinx/common/pm_service/pm_ipi.c \ 124 ${PLAT_PATH}/plat_psci_pm.c \ 125 plat/xilinx/common/pm_service/pm_svc_main.c \ 126 ${PLAT_PATH}/pm_service/pm_client.c \ 127 ${PLAT_PATH}/versal_net_ipi.c 128else 129BL31_SOURCES += ${PLAT_PATH}/plat_psci.c 130endif 131BL31_SOURCES += plat/xilinx/common/plat_fdt.c \ 132 plat/xilinx/common/plat_startup.c \ 133 plat/xilinx/common/plat_console.c \ 134 plat/xilinx/common/plat_clkfunc.c \ 135 plat/xilinx/common/ipi.c \ 136 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ 137 plat/xilinx/common/versal.c \ 138 ${PLAT_PATH}/bl31_versal_net_setup.c \ 139 common/fdt_fixup.c \ 140 common/fdt_wrappers.c \ 141 ${LIBFDT_SRCS} \ 142 ${PLAT_PATH}/sip_svc_setup.c \ 143 ${XLAT_TABLES_LIB_SRCS} 144 145SDEI_SUPPORT := 0 146EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT) 147ifeq (${SDEI_SUPPORT},1) 148BL31_SOURCES += plat/common/aarch64/plat_ehf.c \ 149 plat/xilinx/versal_net/versal_net_sdei.c 150endif 151