Merge "refactor: digest sizes" into integration

Merge changes I1df23bfa,Ibc85e30c into integration

* changes:
fix(st): support device tree DDR sizes higher than 16Gbits for aarch64
feat(fdt-wrappers): add function to read uint64 with default

Merge changes I1df23bfa,Ibc85e30c into integration

* changes:
fix(st): support device tree DDR sizes higher than 16Gbits for aarch64
feat(fdt-wrappers): add function to read uint64 with default value

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refactor: digest sizes

The digest size in bytes for sha1/256/384/512 were defined in multiple
places. Refactor the macros into a common header file.

Change-Id: I84ef3561486ff70345ae8c871d5d6e156457

refactor: digest sizes

The digest size in bytes for sha1/256/384/512 were defined in multiple
places. Refactor the macros into a common header file.

Change-Id: I84ef3561486ff70345ae8c871d5d6e1564574ec2
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>

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fix(cpus): workaround for Cortex-X4 erratum 3076789

Cortex-X4 erratum 3076789 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set chicken bits

fix(cpus): workaround for Cortex-X4 erratum 3076789

Cortex-X4 erratum 3076789 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set chicken bits CPUACTLR3_EL1[14:13]=0b11
and CPUACTLR_EL1[52] = 1.
Expected performance degradation is < 0.5%, but isolated
benchmark components might see higher impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: Ib100bfab91efdb6330fdcdac127bcc5732d59196
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition

feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition 0, is also connected to this IP block. Therefore, all the
dependencies mentioned above must be configured to have a working clock.

Change-Id: Ia841428db9acb95c59ea851b6afeb0b7ff9230a2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi

feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add partitions objects

The S32CC-based SoCs are organized in partitions. These are
software-resettable domains in which configuration participates in
MC_CGM, MC_ME, and RDC modules. A

feat(nxp-clk): add partitions objects

The S32CC-based SoCs are organized in partitions. These are
software-resettable domains in which configuration participates in
MC_CGM, MC_ME, and RDC modules. A partition is an island that may
contain multiple blocks, each of which corresponds to a peripheral or a
core and can, in most cases, be reset individually. This reset structure
results in better device availability. If a fault is detected in a
software reset domain, that domain can be reset separately without
impacting the operation of the rest of the chip.

Change-Id: Ie60dbe151309209e377aa71356dbbd6a4f376a8c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(arm): add support for loading CONFIG from BL2

This commit introduces a new ARM platform-specific build option called
`ARM_FW_CONFIG_LOAD_ENABLE`. This option enables the loading of the
`fw_conf

feat(arm): add support for loading CONFIG from BL2

This commit introduces a new ARM platform-specific build option called
`ARM_FW_CONFIG_LOAD_ENABLE`. This option enables the loading of the
`fw_config` device tree when resetting to the BL2 scenario.

Additionally, the FW_CONFIG image reference has been added to the
fdts/tbbr_cot_descriptors.dtsi file in order to use in the scenario of
RESET_TO_BL2.

Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: I11de497b7dbb1386ed84d939d6fd2a11856e9e1b

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fix(cpus): workaround for Cortex-X4 erratum 2897503

Cortex-X4 erratum 2897503 is a Cat B erratum that applies
to all revisions <= r0p1 and is fixed in r0p2.

The workaround is to set CPUACTLR4_EL1[8

fix(cpus): workaround for Cortex-X4 erratum 2897503

Cortex-X4 erratum 2897503 is a Cat B erratum that applies
to all revisions <= r0p1 and is fixed in r0p2.

The workaround is to set CPUACTLR4_EL1[8] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3178a890b6f1307b310e817af75f8fdfb8668cc9

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Merge changes from topic "nxp-drivers/add-get-parent-callback" into integration

* changes:
feat(nxp-clk): refactor clock enablement
feat(nxp-clk): add get_parent callback
fix(nxp-clk): broken

Merge changes from topic "nxp-drivers/add-get-parent-callback" into integration

* changes:
feat(nxp-clk): refactor clock enablement
feat(nxp-clk): add get_parent callback
fix(nxp-clk): broken UART clock initalization

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feat(fdt-wrappers): add function to read uint64 with default value

Adds a new utility function fdt_read_uint64_default() to read a uint64
value with a default value, as it is already done for uint32

feat(fdt-wrappers): add function to read uint64 with default value

Adds a new utility function fdt_read_uint64_default() to read a uint64
value with a default value, as it is already done for uint32.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ibc85e30c3e4dd4b5171bdec106f4e32eb78c579f

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feat(st-pmic): add STPMIC2 driver

The STPMIC2 embeds 15 regulators with various
properties, and is designed to supply the STM32MP2
SOC. This driver handles a minimal set of feature
to handle the boo

feat(st-pmic): add STPMIC2 driver

The STPMIC2 embeds 15 regulators with various
properties, and is designed to supply the STM32MP2
SOC. This driver handles a minimal set of feature
to handle the boot of a board.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ibe0cacf8aec2871eb9a86ec16cbbd18d3745fe9e

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feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type

feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type. Usually, this is determined based on the parent
field, but not always.

Change-Id: I76a3d2636dc23ba2d547d058b8650dd0e99fe1fa
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration

* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat

Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration

* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat(stm32mp2): add RISAB registers description
feat(stm32mp2-fdts): add BL31 info in fw-config
feat(stm32mp2): add minimal support for BL31
feat(st): manage BL31 FCONF load_info struct

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feat(stm32mp2): add RISAB registers description

Describe the RISAB (Resource isolation slave unit for address space
protection (block-based)) peripheral registers.

Change-Id: I613a52ae6d94264137378

feat(stm32mp2): add RISAB registers description

Describe the RISAB (Resource isolation slave unit for address space
protection (block-based)) peripheral registers.

Change-Id: I613a52ae6d94264137378b805119d38ee59ae762
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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Merge "refactor(rmmd): plat token requests in pieces" into integration

refactor(rmmd): plat token requests in pieces

Until now, the attestation token size was limited by the size of the
shared buffer between RMM and TF-A. With this change, RMM can now
request the token

refactor(rmmd): plat token requests in pieces

Until now, the attestation token size was limited by the size of the
shared buffer between RMM and TF-A. With this change, RMM can now
request the token in pieces, so they fit in the shared buffer. A new
output parameter was added to the SMC call, which will return (along
with the size of bytes copied into the buffer) the number of bytes
of the token that remain to be retrieved.

TF-A will keep an offset variable that will indicate the position in
the token where the next call will retrieve bytes from. This offset
will be increased on every call by adding the number number of bytes
copied. If the received hash size is not 0, TF-A will reset the
offset to 0 and copy from that position on.

The SMC call will now return at most the size of the shared buffer
in bytes on every call. Therefore, from now on, multiple SMC calls
may be needed to be issued if the token size exceeds the shared
buffer size.

Change-Id: I591f7013d06f64e98afaf9535dbea6f815799723
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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fix(gicv3): fix GITS_CTLR.Quiescent bit definition

GITS_CTLR.Quiescent is bit31, not bit1.
So fix GITS_CTLR_QUIESCENT_BIT to BIT32(31).

Change-Id: Ic16a52e0c4e557d68a8128ccc7e7a0f1a316a23b
Signed-o

fix(gicv3): fix GITS_CTLR.Quiescent bit definition

GITS_CTLR.Quiescent is bit31, not bit1.
So fix GITS_CTLR_QUIESCENT_BIT to BIT32(31).

Change-Id: Ic16a52e0c4e557d68a8128ccc7e7a0f1a316a23b
Signed-off-by: Joe Yang <magicse7en@outlook.com>

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feat(cm): handle asymmetry for FEAT_TCR2

With introduction of FEAT_STATE_CHECK_ASYMMETRIC, the asymmetry of cores
can be handled. FEAT_TCR2 is one of the features which can be
asymmetric across core

feat(cm): handle asymmetry for FEAT_TCR2

With introduction of FEAT_STATE_CHECK_ASYMMETRIC, the asymmetry of cores
can be handled. FEAT_TCR2 is one of the features which can be
asymmetric across cores and the respective support is added here.

Adding a function to handle this asymmetry by re-visting the
feature presence on running core.
There are two possible cases:
- If the primary core has the feature and secondary does not have it
then the feature is disabled.
- If the primary does not have the feature and secondary has it then,
the feature need to be enabled in secondary cores.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I73a70891d52268ddfa4effe40edf04115f5821ca

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chore(mbedtls): remove hash configs

After the upgrade to mbedtls 3.6.0, some of these configuation limitations
are no longer present.

Size chages:
build config | executable | Delta
-------------|--

chore(mbedtls): remove hash configs

After the upgrade to mbedtls 3.6.0, some of these configuation limitations
are no longer present.

Size chages:
build config | executable | Delta
-------------|------------|-------
tbb ecdsa | bl1 | -176
-------------|------------|-------
tbb rsa | bl1 | -192
| bl2 | -4096
-------------|------------|-------
drtm | romlib | -576
-------------|------------|-------
spm | romlib | -576
-------------|------------|-------
mb384 | romlib | -1016

Change-Id: I019bc59adc93cf95f6f28ace9579e7bf1e785b62
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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Merge changes from topic "clean-up-errata-compatibility" into integration

* changes:
refactor(cpus): remove cpu specific errata funcs
refactor(cpus): directly invoke errata reporter

Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config fil

Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1
feat(stm32mp2-fdts): add fw-config file
feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1
feat(stm32mp2): enable DDR sub-system clock
feat(stm32mp2): add fixed regulators support
feat(stm32mp2): print board info
feat(stm32mp2): display CPU info
feat(stm32mp2): get chip ID
feat(stm32mp2): add BL2 boot first steps
feat(stm32mp2): add defines for the PWR peripheral
feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1
feat(stm32mp2-fdts): add sdmmc pins definition
feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file
feat(stm32mp2-fdts): add io_policies
feat(stm32mp2-fdts): remove pins-are-numbered

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Merge changes from topic "nxp-drivers/add-linflex-clk" into integration

* changes:
feat(nxp-clk): enable UART clock
feat(nxp-clk): add PERIPH PLL enablement

refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1

* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure,

refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1

* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure, we hold a copy of EL1, EL2
system registers, per world per PE. This context structure is
enormous and will continue to grow bigger with the addition of
new features incorporating new registers.

* Ideally, EL3 should save and restore the system registers at its next
lower exception level, which is EL2 in majority of the configurations.

* This patch aims at optimising the memory allocation in cases, when
the members from the context structure are unused. So el1 system
register context must be omitted when lower EL is always x-EL2.

* "CTX_INCLUDE_EL2_REGS" is the internal build flag which gets set,
when SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1.
It indicates, the system registers at EL2 are context switched for
the respective build configuration. Here, there is no need to save
and restore EL1 system registers, while x-EL2 is enabled.

Henceforth, this patch addresses this issue, by taking out the EL1
context at all possible places, while EL2 (CTX_INCLUDE_EL2_REGS) is
enabled, there by saving memory.

Change-Id: Ifddc497d3c810e22a15b1c227a731bcc133c2f4a
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to wr

chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to write and read into these context entries, looks
repetitive and is invoked at most places.
This section is refactored to bring them under a static procedure,
keeping the code neat and easier to maintain.

Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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