History log of /rk3399_ARM-atf/include/ (Results 3126 – 3150 of 3957)
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f9a6db0f03-Nov-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1151 from JoelHutton/jh/MISRA-Mandatory

Change sizeof to use type of struct not function

3de7d58e03-Nov-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1137 from soby-mathew/sm/arm_plat_en_gicv3_save

Enable GICv3 save for ARM platforms

122af7dd01-Nov-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1150 from dp-arm/dp/events

aarch64: Add PubSub events to capture security state transitions

e8a87acd23-Oct-2017 Roberto Vargas <roberto.vargas@arm.com>

Fix usage of IMAGE_BLx macros

These macros are only defined for corresponding image,
and they are undefined for other images. It means that we have
to use ifdef or defined() instead of relying on be

Fix usage of IMAGE_BLx macros

These macros are only defined for corresponding image,
and they are undefined for other images. It means that we have
to use ifdef or defined() instead of relying on being 0 by default.

Change-Id: Iad11efab9830ddf471599b46286e1c56581ef5a7
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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27b2493c31-Oct-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1141 from robertovargas-arm/boot_redundancy

Add platform hooks for boot redundancy support

2614ea3e20-Oct-2017 Joel Hutton <joel.hutton@arm.com>

Change sizeof to use type of struct not function

Change sizeof call so it references a static type instead of return of
a function in order to be MISRA compliant.

Change-Id: I6f1adb206073d6cd200156

Change sizeof to use type of struct not function

Change sizeof call so it references a static type instead of return of
a function in order to be MISRA compliant.

Change-Id: I6f1adb206073d6cd200156e281b8d76249e3af0e
Signed-off-by: Joel Hutton <joel.hutton@arm.com>

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17b4c0dd13-Oct-2017 Dimitris Papastamos <dimitris.papastamos@arm.com>

aarch64: Add PubSub events to capture security state transitions

Add events that trigger before entry to normal/secure world. The
events trigger after the normal/secure context has been restored.

aarch64: Add PubSub events to capture security state transitions

Add events that trigger before entry to normal/secure world. The
events trigger after the normal/secure context has been restored.

Similarly add events that trigger after leaving normal/secure world.
The events trigger after the normal/secure context has been saved.

Change-Id: I1b48a7ea005d56b1f25e2b5313d77e67d2f02bc5
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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9b1eae9613-Oct-2017 Qixiang Xu <qixiang.xu@arm.com>

plat/arm: enlarge the BL2 size on Arm platforms when TBB is enabled

For Trusted Board Boot, BL2 needs more space to support the ECDSA
and ECDSA+RSA algorithms.

Change-Id: Ie7eda9a1315ce836dbc6d18d6

plat/arm: enlarge the BL2 size on Arm platforms when TBB is enabled

For Trusted Board Boot, BL2 needs more space to support the ECDSA
and ECDSA+RSA algorithms.

Change-Id: Ie7eda9a1315ce836dbc6d18d6588f8d17891a92d
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>

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01f62b6d26-Sep-2017 Roberto Vargas <roberto.vargas@arm.com>

Add platform hooks for boot redundancy support

These hooks are intended to allow one platform to try load
images from alternative places. There is a hook to initialize
the sequence of boot locations

Add platform hooks for boot redundancy support

These hooks are intended to allow one platform to try load
images from alternative places. There is a hook to initialize
the sequence of boot locations and a hook to pass to the next
sequence.

Change-Id: Ia0f84c415208dc4fa4f9d060d58476db23efa5b2
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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bd0c347722-Sep-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

PSCI: Publish CPU ON event

This allows other EL3 components to subscribe to CPU on events.

Update Firmware Design guide to list psci_cpu_on_finish as an available
event.

Change-Id: Ida774afe0f9cdc

PSCI: Publish CPU ON event

This allows other EL3 components to subscribe to CPU on events.

Update Firmware Design guide to list psci_cpu_on_finish as an available
event.

Change-Id: Ida774afe0f9cdce4021933fcc33a9527ba7aaae2
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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8e743bcd22-Sep-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

BL31: Introduce Publish and Subscribe framework

This light-weight framework enables some EL3 components to publish
events which other EL3 components can subscribe to. Publisher can
optionally pass o

BL31: Introduce Publish and Subscribe framework

This light-weight framework enables some EL3 components to publish
events which other EL3 components can subscribe to. Publisher can
optionally pass opaque data for subscribers. The order in which
subscribers are called is not defined.

Firmware design updated.

Change-Id: I24a3a70b2b1dedcb1f73cf48313818aebf75ebb6
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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f911e22921-Oct-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1131 from jeenu-arm/gic-migrate

Migrate upstream platforms to using interrupt properties

623c437721-Oct-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1130 from jeenu-arm/gic-patches

New GIC APIs and specifying interrupt propertes

8b9f419e20-Oct-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1136 from antonio-nino-diaz-arm/an/xlat-get-set-attr

Add APIs to get and modify attributes of memory regions

b4e81a3318-Oct-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1129 from robertovargas-arm/enable_O0

Fix use of MSR (immediate)

ccd0c24c17-Oct-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1127 from davidcunado-arm/dc/pmrc_init

Init and save / restore of PMCR_EL0 / PMCR

5d2f87e817-Oct-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1126 from robertovargas-arm/psci-v1.1

Update PSCI to v1.1

ec0c8fda05-Oct-2017 Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Introduce functions to disable the MMU in EL1

The implementation is the same as those used to disable it in EL3.

Change-Id: Ibfe7e69034a691fbf57477c5a76a8cdca28f6b26
Signed-off-by: Antonio Nino Dia

Introduce functions to disable the MMU in EL1

The implementation is the same as those used to disable it in EL3.

Change-Id: Ibfe7e69034a691fbf57477c5a76a8cdca28f6b26
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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996d6b3917-Oct-2017 Sandrine Bailleux <sandrine.bailleux@arm.com>

xlat: Introduce API to change memory attributes of a region

This patch introduces a new API in the translation tables library
(v2), that allows to change the memory attributes of a memory
region. It

xlat: Introduce API to change memory attributes of a region

This patch introduces a new API in the translation tables library
(v2), that allows to change the memory attributes of a memory
region. It may be used to change its execution permissions and
data access permissions.

As a prerequisite, the memory must be already mapped. Moreover, it
must be mapped at the finest granularity (currently 4 KB).

Change-Id: I242a8c6f0f3ef2b0a81a61e28706540462faca3c
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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1be910bb13-Oct-2017 Sandrine Bailleux <sandrine.bailleux@arm.com>

xlat: Introduce API to get memory attributes of a region

This patch introduces a new API in the translation tables library
(v2), that allows to query the memory attributes of a memory block
or a mem

xlat: Introduce API to get memory attributes of a region

This patch introduces a new API in the translation tables library
(v2), that allows to query the memory attributes of a memory block
or a memory page.

Change-Id: I45a8b39a53da39e7617cbac4bff5658dc1b20a11
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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8bf5bac816-Oct-2017 Antonio Nino Diaz <antonio.ninodiaz@arm.com>

xlat: Define translation regime in AArch32

Previously, in AArch32, `IMAGE_XLAT_DEFAULT_REGIME` wasn't defined. The
translation regime is only used in the AArch64 port of the translation
tables libra

xlat: Define translation regime in AArch32

Previously, in AArch32, `IMAGE_XLAT_DEFAULT_REGIME` wasn't defined. The
translation regime is only used in the AArch64 port of the translation
tables library v2, so this is not a problem for now, but future patches
will use it.

`IMAGE_EL` isn't used in AArch32, so it isn't needed to define it.

Change-Id: I4acdb01a58658956ab94bd82ed5b7fee1aa6ba90
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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c639e8eb22-Sep-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

GIC: Allow specifying interrupt properties

The GIC driver initialization currently allows an array of interrupts to
be configured as secure. Future use cases would require more interrupt
configurati

GIC: Allow specifying interrupt properties

The GIC driver initialization currently allows an array of interrupts to
be configured as secure. Future use cases would require more interrupt
configuration other than just security, such as priority.

This patch introduces a new interrupt property array as part of both
GICv2 and GICv3 driver data. The platform can populate the array with
interrupt numbers and respective properties. The corresponding driver
initialization iterates through the array, and applies interrupt
configuration as required.

This capability, and the current way of supplying array (or arrays, in
case of GICv3) of secure interrupts, are however mutually exclusive.
Henceforth, the platform should supply either:

- A list of interrupts to be mapped as secure (the current way).
Platforms that do this will continue working as they were. With this
patch, this scheme is deprecated.

- A list of interrupt properties (properties include interrupt group).
Individual interrupt properties are specified via. descriptors of
type 'interrupt_prop_desc_t', which can be populated with the macro
INTR_PROP_DESC().

A run time assert checks that the platform doesn't specify both.

Henceforth the old scheme of providing list of secure interrupts is
deprecated. When built with ERROR_DEPRECATED=1, GIC drivers will require
that the interrupt properties are supplied instead of an array of secure
interrupts.

Add a section to firmware design about configuring secure interrupts.

Fixes ARM-software/tf-issues#262

Change-Id: I8eec29e72eb69dbb6bce77879febf32c95376942
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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2296610622-Sep-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

GIC: Add helpers to set interrupt configuration

The helpers perform read-modify-write on GIC*_ICFGR registers, but don't
serialise callers. Any serialisation must be taken care of by the
callers.

C

GIC: Add helpers to set interrupt configuration

The helpers perform read-modify-write on GIC*_ICFGR registers, but don't
serialise callers. Any serialisation must be taken care of by the
callers.

Change-Id: I71995f82ff2c7f70d37af0ede30d6ee18682fd3f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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b2c363b122-Sep-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

ARM platforms: Migrate to using interrupt properties

An earlier patch added provision for the platform to provide secure
interrupt properties. ARM platforms already has a list of interrupts
that fal

ARM platforms: Migrate to using interrupt properties

An earlier patch added provision for the platform to provide secure
interrupt properties. ARM platforms already has a list of interrupts
that fall into different secure groups.

This patch defines macros that enumerate interrupt properties in the
same fashion, and points the driver driver data to a list of interrupt
properties rather than list of secure interrupts on ARM platforms. The
deprecated interrupt list definitions are however retained to support
legacy builds.

Configuration applied to individual interrupts remain unchanged, so no
runtime behaviour change expected.

NOTE: Platforms that use the arm/common function
plat_arm_gic_driver_init() must replace their PLAT_ARM_G1S_IRQS and
PLAT_ARM_G0_IRQS macro definitions with PLAT_ARM_G1S_IRQ_PROPS and
PLAT_ARM_G0_IRQ_PROPS macros respectively, using the provided
INTR_PROP_DESC macro.

Change-Id: I24d643b83e3333753a3ba97d4b6fb71e16bb0952
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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d55a445022-Sep-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

GIC: Add API to set priority mask

API documentation updated.

Change-Id: I40feec1fe67a960d035061b54dd55610bc34ce1d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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