1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12#include <cortex_a75.h> 13 14 .globl cortex_a75_amu_cnt_read 15 .globl cortex_a75_amu_cnt_write 16 .globl cortex_a75_amu_read_cpuamcntenset_el0 17 .globl cortex_a75_amu_read_cpuamcntenclr_el0 18 .globl cortex_a75_amu_write_cpuamcntenset_el0 19 .globl cortex_a75_amu_write_cpuamcntenclr_el0 20 21/* 22 * uint64_t cortex_a75_amu_cnt_read(int idx); 23 * 24 * Given `idx`, read the corresponding AMU counter 25 * and return it in `x0`. 26 */ 27func cortex_a75_amu_cnt_read 28 adr x1, 1f 29 lsl x0, x0, #3 30 add x1, x1, x0 31 br x1 32 331: 34 mrs x0, CPUAMEVCNTR0_EL0 35 ret 36 mrs x0, CPUAMEVCNTR1_EL0 37 ret 38 mrs x0, CPUAMEVCNTR2_EL0 39 ret 40 mrs x0, CPUAMEVCNTR3_EL0 41 ret 42 mrs x0, CPUAMEVCNTR4_EL0 43 ret 44endfunc cortex_a75_amu_cnt_read 45 46/* 47 * void cortex_a75_amu_cnt_write(int idx, uint64_t val); 48 * 49 * Given `idx`, write `val` to the corresponding AMU counter. 50 */ 51func cortex_a75_amu_cnt_write 52 adr x2, 1f 53 lsl x0, x0, #3 54 add x2, x2, x0 55 br x2 56 571: 58 msr CPUAMEVCNTR0_EL0, x0 59 ret 60 msr CPUAMEVCNTR1_EL0, x0 61 ret 62 msr CPUAMEVCNTR2_EL0, x0 63 ret 64 msr CPUAMEVCNTR3_EL0, x0 65 ret 66 msr CPUAMEVCNTR4_EL0, x0 67 ret 68endfunc cortex_a75_amu_cnt_write 69 70/* 71 * unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void); 72 * 73 * Read the `CPUAMCNTENSET_EL0` CPU register and return 74 * it in `x0`. 75 */ 76func cortex_a75_amu_read_cpuamcntenset_el0 77 mrs x0, CPUAMCNTENSET_EL0 78 ret 79endfunc cortex_a75_amu_read_cpuamcntenset_el0 80 81/* 82 * unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void); 83 * 84 * Read the `CPUAMCNTENCLR_EL0` CPU register and return 85 * it in `x0`. 86 */ 87func cortex_a75_amu_read_cpuamcntenclr_el0 88 mrs x0, CPUAMCNTENCLR_EL0 89 ret 90endfunc cortex_a75_amu_read_cpuamcntenclr_el0 91 92/* 93 * void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask); 94 * 95 * Write `mask` to the `CPUAMCNTENSET_EL0` CPU register. 96 */ 97func cortex_a75_amu_write_cpuamcntenset_el0 98 msr CPUAMCNTENSET_EL0, x0 99 ret 100endfunc cortex_a75_amu_write_cpuamcntenset_el0 101 102/* 103 * void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask); 104 * 105 * Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register. 106 */ 107func cortex_a75_amu_write_cpuamcntenclr_el0 108 mrs x0, CPUAMCNTENCLR_EL0 109 ret 110endfunc cortex_a75_amu_write_cpuamcntenclr_el0 111 112func cortex_a75_reset_func 113#if ENABLE_AMU 114 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 115 mrs x0, actlr_el3 116 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 117 msr actlr_el3, x0 118 isb 119 120 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 121 mrs x0, actlr_el2 122 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 123 msr actlr_el2, x0 124 isb 125 126 /* Enable group0 counters */ 127 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 128 msr CPUAMCNTENSET_EL0, x0 129 isb 130 131 /* Enable group1 counters */ 132 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 133 msr CPUAMCNTENSET_EL0, x0 134 isb 135#endif 136 ret 137endfunc cortex_a75_reset_func 138 139 /* --------------------------------------------- 140 * HW will do the cache maintenance while powering down 141 * --------------------------------------------- 142 */ 143func cortex_a75_core_pwr_dwn 144 /* --------------------------------------------- 145 * Enable CPU power down bit in power control register 146 * --------------------------------------------- 147 */ 148 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 149 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 150 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 151 isb 152 ret 153endfunc cortex_a75_core_pwr_dwn 154 155 /* --------------------------------------------- 156 * This function provides cortex_a75 specific 157 * register information for crash reporting. 158 * It needs to return with x6 pointing to 159 * a list of register names in ascii and 160 * x8 - x15 having values of registers to be 161 * reported. 162 * --------------------------------------------- 163 */ 164.section .rodata.cortex_a75_regs, "aS" 165cortex_a75_regs: /* The ascii list of register names to be reported */ 166 .asciz "cpuectlr_el1", "" 167 168func cortex_a75_cpu_reg_dump 169 adr x6, cortex_a75_regs 170 mrs x8, CORTEX_A75_CPUECTLR_EL1 171 ret 172endfunc cortex_a75_cpu_reg_dump 173 174declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \ 175 cortex_a75_reset_func, \ 176 cortex_a75_core_pwr_dwn 177