xref: /rk3399_ARM-atf/bl2/bl2_el3.ld.S (revision b1d27b484f4172542eca074fdac42ffd13736a0f) 
1/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8#include <xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
16}
17
18
19SECTIONS
20{
21    . = BL2_BASE;
22    ASSERT(. == ALIGN(PAGE_SIZE),
23           "BL2_BASE address is not aligned on a page boundary.")
24
25#if SEPARATE_CODE_AND_RODATA
26    .text . : {
27        __TEXT_START__ = .;
28        *bl2_el3_entrypoint.o(.text*)
29        *(.text*)
30        *(.vectors)
31        . = NEXT(PAGE_SIZE);
32        __TEXT_END__ = .;
33     } >RAM
34
35    .rodata . : {
36        __RODATA_START__ = .;
37        *(.rodata*)
38
39        /* Ensure 8-byte alignment for descriptors and ensure inclusion */
40        . = ALIGN(8);
41        __PARSER_LIB_DESCS_START__ = .;
42        KEEP(*(.img_parser_lib_descs))
43        __PARSER_LIB_DESCS_END__ = .;
44
45        /*
46         * Ensure 8-byte alignment for cpu_ops so that its fields are also
47         * aligned. Also ensure cpu_ops inclusion.
48         */
49        . = ALIGN(8);
50        __CPU_OPS_START__ = .;
51        KEEP(*(cpu_ops))
52        __CPU_OPS_END__ = .;
53
54        . = NEXT(PAGE_SIZE);
55        __RODATA_END__ = .;
56    } >RAM
57#else
58    ro . : {
59        __RO_START__ = .;
60        *bl2_el3_entrypoint.o(.text*)
61        *(.text*)
62        *(.rodata*)
63
64        /*
65         * Ensure 8-byte alignment for cpu_ops so that its fields are also
66         * aligned. Also ensure cpu_ops inclusion.
67         */
68        . = ALIGN(8);
69        __CPU_OPS_START__ = .;
70        KEEP(*(cpu_ops))
71        __CPU_OPS_END__ = .;
72
73        /* Ensure 8-byte alignment for descriptors and ensure inclusion */
74        . = ALIGN(8);
75        __PARSER_LIB_DESCS_START__ = .;
76        KEEP(*(.img_parser_lib_descs))
77        __PARSER_LIB_DESCS_END__ = .;
78
79        *(.vectors)
80        __RO_END_UNALIGNED__ = .;
81        /*
82         * Memory page(s) mapped to this section will be marked as
83         * read-only, executable.  No RW data from the next section must
84         * creep in.  Ensure the rest of the current memory page is unused.
85         */
86        . = NEXT(PAGE_SIZE);
87
88        __RO_END__ = .;
89    } >RAM
90#endif
91
92    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
93          "cpu_ops not defined for this platform.")
94
95    /*
96     * Define a linker symbol to mark start of the RW memory area for this
97     * image.
98     */
99    __RW_START__ = . ;
100
101    /*
102     * .data must be placed at a lower address than the stacks if the stack
103     * protector is enabled. Alternatively, the .data.stack_protector_canary
104     * section can be placed independently of the main .data section.
105     */
106    .data . : {
107        __DATA_START__ = .;
108        *(.data*)
109        __DATA_END__ = .;
110    } >RAM
111
112    stacks (NOLOAD) : {
113        __STACKS_START__ = .;
114        *(tzfw_normal_stacks)
115        __STACKS_END__ = .;
116    } >RAM
117
118    /*
119     * The .bss section gets initialised to 0 at runtime.
120     * Its base address should be 16-byte aligned for better performance of the
121     * zero-initialization code.
122     */
123    .bss : ALIGN(16) {
124        __BSS_START__ = .;
125        *(SORT_BY_ALIGNMENT(.bss*))
126        *(COMMON)
127        __BSS_END__ = .;
128    } >RAM
129
130    /*
131     * The xlat_table section is for full, aligned page tables (4K).
132     * Removing them from .bss avoids forcing 4K alignment on
133     * the .bss section and eliminates the unnecessary zero init
134     */
135    xlat_table (NOLOAD) : {
136        *(xlat_table)
137    } >RAM
138
139#if USE_COHERENT_MEM
140    /*
141     * The base address of the coherent memory section must be page-aligned (4K)
142     * to guarantee that the coherent data are stored on their own pages and
143     * are not mixed with normal data.  This is required to set up the correct
144     * memory attributes for the coherent data page tables.
145     */
146    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
147        __COHERENT_RAM_START__ = .;
148        *(tzfw_coherent_mem)
149        __COHERENT_RAM_END_UNALIGNED__ = .;
150        /*
151         * Memory page(s) mapped to this section will be marked
152         * as device memory.  No other unexpected data must creep in.
153         * Ensure the rest of the current memory page is unused.
154         */
155        . = NEXT(PAGE_SIZE);
156        __COHERENT_RAM_END__ = .;
157    } >RAM
158#endif
159
160    /*
161     * Define a linker symbol to mark end of the RW memory area for this
162     * image.
163     */
164    __RW_END__ = .;
165    __BL2_END__ = .;
166
167    __BSS_SIZE__ = SIZEOF(.bss);
168
169#if USE_COHERENT_MEM
170    __COHERENT_RAM_UNALIGNED_SIZE__ =
171        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
172#endif
173
174    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
175}
176