1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12#include <cortex_a75.h> 13 14func cortex_a75_reset_func 15#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 16 adr x0, workaround_bpiall_vbar0_runtime_exceptions 17 msr vbar_el3, x0 18#endif 19 20#if ENABLE_AMU 21 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 22 mrs x0, actlr_el3 23 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 24 msr actlr_el3, x0 25 isb 26 27 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 28 mrs x0, actlr_el2 29 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 30 msr actlr_el2, x0 31 isb 32 33 /* Enable group0 counters */ 34 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 35 msr CPUAMCNTENSET_EL0, x0 36 isb 37 38 /* Enable group1 counters */ 39 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 40 msr CPUAMCNTENSET_EL0, x0 41 isb 42#endif 43 ret 44endfunc cortex_a75_reset_func 45 46 /* --------------------------------------------- 47 * HW will do the cache maintenance while powering down 48 * --------------------------------------------- 49 */ 50func cortex_a75_core_pwr_dwn 51 /* --------------------------------------------- 52 * Enable CPU power down bit in power control register 53 * --------------------------------------------- 54 */ 55 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 56 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 57 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 58 isb 59 ret 60endfunc cortex_a75_core_pwr_dwn 61 62 /* --------------------------------------------- 63 * This function provides cortex_a75 specific 64 * register information for crash reporting. 65 * It needs to return with x6 pointing to 66 * a list of register names in ascii and 67 * x8 - x15 having values of registers to be 68 * reported. 69 * --------------------------------------------- 70 */ 71.section .rodata.cortex_a75_regs, "aS" 72cortex_a75_regs: /* The ascii list of register names to be reported */ 73 .asciz "cpuectlr_el1", "" 74 75func cortex_a75_cpu_reg_dump 76 adr x6, cortex_a75_regs 77 mrs x8, CORTEX_A75_CPUECTLR_EL1 78 ret 79endfunc cortex_a75_cpu_reg_dump 80 81declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \ 82 cortex_a75_reset_func, \ 83 cortex_a75_core_pwr_dwn 84