1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12#include <cortex_a75.h> 13 14func cortex_a75_reset_func 15#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 16 mrs x0, id_aa64pfr0_el1 17 ubfx x0, x0, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH 18 /* 19 * If the field equals to 1 then branch targets trained in one 20 * context cannot affect speculative execution in a different context. 21 */ 22 cmp x0, #1 23 beq 1f 24 25 adr x0, workaround_bpiall_vbar0_runtime_exceptions 26 msr vbar_el3, x0 271: 28#endif 29 30#if ENABLE_AMU 31 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 32 mrs x0, actlr_el3 33 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 34 msr actlr_el3, x0 35 isb 36 37 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 38 mrs x0, actlr_el2 39 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 40 msr actlr_el2, x0 41 isb 42 43 /* Enable group0 counters */ 44 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 45 msr CPUAMCNTENSET_EL0, x0 46 isb 47 48 /* Enable group1 counters */ 49 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 50 msr CPUAMCNTENSET_EL0, x0 51 isb 52#endif 53 ret 54endfunc cortex_a75_reset_func 55 56 /* --------------------------------------------- 57 * HW will do the cache maintenance while powering down 58 * --------------------------------------------- 59 */ 60func cortex_a75_core_pwr_dwn 61 /* --------------------------------------------- 62 * Enable CPU power down bit in power control register 63 * --------------------------------------------- 64 */ 65 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 66 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 67 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 68 isb 69 ret 70endfunc cortex_a75_core_pwr_dwn 71 72 /* --------------------------------------------- 73 * This function provides cortex_a75 specific 74 * register information for crash reporting. 75 * It needs to return with x6 pointing to 76 * a list of register names in ascii and 77 * x8 - x15 having values of registers to be 78 * reported. 79 * --------------------------------------------- 80 */ 81.section .rodata.cortex_a75_regs, "aS" 82cortex_a75_regs: /* The ascii list of register names to be reported */ 83 .asciz "cpuectlr_el1", "" 84 85func cortex_a75_cpu_reg_dump 86 adr x6, cortex_a75_regs 87 mrs x8, CORTEX_A75_CPUECTLR_EL1 88 ret 89endfunc cortex_a75_cpu_reg_dump 90 91declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \ 92 cortex_a75_reset_func, \ 93 cortex_a75_core_pwr_dwn 94