| c6213c7e | 11-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat/arm: Reduce size of BL31 binary" into integration |
| 5e4c97d0 | 25-Jun-2019 |
Stefan Chulski <stefanc@marvell.com> |
plat: marvell: ap807: implement workaround for errata-id 3033912
ERRATA ID: RES-3033912 - Internal Address Space Init state causes
a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
Workaround: Boot
plat: marvell: ap807: implement workaround for errata-id 3033912
ERRATA ID: RES-3033912 - Internal Address Space Init state causes
a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
[0x80_0000, 0xff_ffff] that cause accesses to the segment of
[0xf070_0000, 0xf07f_ffff] to act as RAZWI. Reuse common
work-around code for both AP806 and AP807.
Change-Id: Ia91a4802d02917d1682faa0c81571093d1687d97
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
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|
| 8f09da46 | 10-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "release/14.0" into integration
* changes:
docs: marvell: update PHY porting layer description
docs: marvell: update path in marvell documentation
docs: marvell: updat
Merge changes from topic "release/14.0" into integration
* changes:
docs: marvell: update PHY porting layer description
docs: marvell: update path in marvell documentation
docs: marvell: update build instructions with CN913x
plat: marvell: octeontx: add support for t9130
plat: marvell: t9130: add SVC support
plat: marvell: t9130: update AVS settings
plat: marvell: t9130: pass actual CP count for load_image
plat: marvell: armada: a7k: add support to SVC validation mode
plat: marvell: armada: add support for twin-die combined memory device
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|
| f3ccf036 | 14-Jul-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A AMU extension: fix detection of group 1 counters.
This patch fixes the bug when AMUv1 group1 counters was
always assumed being implemented without checking for its
presence which was causing ex
TF-A AMU extension: fix detection of group 1 counters.
This patch fixes the bug when AMUv1 group1 counters was
always assumed being implemented without checking for its
presence which was causing exception otherwise.
The AMU extension code was also modified as listed below:
- Added detection of AMUv1 for ARMv8.6
- 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and
number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now
calculated based on 'AMU_GROUP1_COUNTERS_MASK' value
- Added bit fields definitions and access functions for
AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers
- Unification of amu.c Aarch64 and Aarch32 source files
- Bug fixes and TF-A coding style compliant changes.
Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| fa1fdb22 | 21-Jul-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
plat/arm: Reduce size of BL31 binary
BL31 binary size is aligned to 4KB because of the
code in include\plat\arm\common\arm_reclaim_init.ld.S:
__INIT_CODE_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE
plat/arm: Reduce size of BL31 binary
BL31 binary size is aligned to 4KB because of the
code in include\plat\arm\common\arm_reclaim_init.ld.S:
__INIT_CODE_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
__INIT_CODE_END__ = .;
with all the zero data after the last instruction of
BL31 code to the end of the page.
This causes increase in size of BL31 binary stored in FIP
and its loading time by BL2.
This patch reduces the size of BL31 image by moving
page alignment from __INIT_CODE_END__ to __STACKS_END__
which also increases the stack size for secondary CPUs.
Change-Id: Ie2ec503fc774c22c12ec506d74fd3ef2b0b183a9
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| a4a9547c | 23-Jul-2019 |
Alex Van Brunt <avanbrunt@nvidia.com> |
lib: cpus: denver: add some MIDR values
This patch adds support for additional Denver MIDRs to
cover all the current SKUs.
Change-Id: I85d0ffe9b3cb351f430ca7d7065a2609968a7a28
Signed-off-by: Alex V
lib: cpus: denver: add some MIDR values
This patch adds support for additional Denver MIDRs to
cover all the current SKUs.
Change-Id: I85d0ffe9b3cb351f430ca7d7065a2609968a7a28
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 070632f9 | 04-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "SPM: build OP-TEE as an S-EL1 Secure Partition" into integration |
| 03a5225c | 23-Jul-2020 |
Manish Pandey <manish.pandey2@arm.com> |
tbbr/dualroot: rename SP package certificate file
Currently only single signing domain is supported for SP packages but
there is plan to support dual signing domains if CoT is dualroot.
SP_CONTENT_
tbbr/dualroot: rename SP package certificate file
Currently only single signing domain is supported for SP packages but
there is plan to support dual signing domains if CoT is dualroot.
SP_CONTENT_CERT_ID is the certificate file which is currently generated
and signed with trusted world key which in-turn is derived from Silicon
provider RoT key.
To allow dual signing domain for SP packages, other certificate file
will be derived from Platform owned RoT key.
This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and
does other related changes.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
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|
| db1ef41a | 01-Apr-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
SPM: build OP-TEE as an S-EL1 Secure Partition
Provide manifest and build options to boot OP-TEE as a
guest S-EL1 Secure Partition on top of Hafnium in S-EL2.
Increase ARM_SP_MAX_SIZE to cope with
SPM: build OP-TEE as an S-EL1 Secure Partition
Provide manifest and build options to boot OP-TEE as a
guest S-EL1 Secure Partition on top of Hafnium in S-EL2.
Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb
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|
| 5bc3643e | 27-Mar-2019 |
Ben Peled <bpeled@marvell.com> |
plat: marvell: t9130: pass actual CP count for load_image
Add CN913x case to bl2_plat_get_cp_count.
Fix loading of cp1/2 image. This is a preparation
patch for adding CN913x SoC family support.
Cha
plat: marvell: t9130: pass actual CP count for load_image
Add CN913x case to bl2_plat_get_cp_count.
Fix loading of cp1/2 image. This is a preparation
patch for adding CN913x SoC family support.
Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9
Signed-off-by: Ben Peled <bpeled@marvell.com>
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|
| b29c350c | 29-Jul-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
GIC-600: Fix MISRA-2012 defects
This patch fixes violation of Rules 10.1, 10.4,
11.9 and 13.2 reported by MISRA-2012 scan.
Change-Id: Ibe9190cb0f26ae85d9a31db8e92fbd32f1740e25
Signed-off-by: Alexei
GIC-600: Fix MISRA-2012 defects
This patch fixes violation of Rules 10.1, 10.4,
11.9 and 13.2 reported by MISRA-2012 scan.
Change-Id: Ibe9190cb0f26ae85d9a31db8e92fbd32f1740e25
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| a6151e7c | 28-Jul-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "SMCCC: Introduce function to check SMCCC function availability" into integration |
| 858e69e8 | 27-Jul-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TZ DMC620 driver: Fix MISRA-2012 defects
This patch fixes defects 10.3, 10.4, 10.7, 20.7
reported by MISRA-2012 scan and adds braces for
conditional statements according to the TF-A
coding style.
C
TZ DMC620 driver: Fix MISRA-2012 defects
This patch fixes defects 10.3, 10.4, 10.7, 20.7
reported by MISRA-2012 scan and adds braces for
conditional statements according to the TF-A
coding style.
Change-Id: If84ed31cdd55bc8e7cdd2a5f48c0dacc25792112
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| 6f0a2f04 | 23-Jul-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
SMCCC: Introduce function to check SMCCC function availability
Currently, 'SMCCC_ARCH_FEATURES' SMC call handler unconditionally
returns 'SMC_OK' for 'SMCCC_ARCH_SOC_ID' function. This seems to
be n
SMCCC: Introduce function to check SMCCC function availability
Currently, 'SMCCC_ARCH_FEATURES' SMC call handler unconditionally
returns 'SMC_OK' for 'SMCCC_ARCH_SOC_ID' function. This seems to
be not correct for the platform which doesn't implement soc-id
functionality i.e. functions to retrieve both soc-version and
soc-revision.
Hence introduced a platform function which will check whether SMCCC
feature is available for the platform.
Also, updated porting guide for the newly added platform function.
Change-Id: I389f0ef6b0837bb24c712aa995b7176117bc7961
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 1056ddce | 23-Jul-2020 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "Revert workaround for Neoverse N1 erratum 1800710" into integration |
| f0bbaebc | 23-Jul-2020 |
johpow01 <john.powell@arm.com> |
Revert workaround for Neoverse N1 erratum 1800710
This reverts commit 11af40b6308ac75c83e874129bb79bc3a58060bf, reversing
changes made to 2afcf1d4b845272791b75c8285108c4dcd91e2b9.
This errata worka
Revert workaround for Neoverse N1 erratum 1800710
This reverts commit 11af40b6308ac75c83e874129bb79bc3a58060bf, reversing
changes made to 2afcf1d4b845272791b75c8285108c4dcd91e2b9.
This errata workaround did not work as intended so we are reverting this
change. In the future, when the corrected workaround is published in an
SDEN, we will push a new workaround.
This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97
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|
| a07c101a | 16-Jul-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
plat/arm: Move fconf population after the enablement of MMU
In BL2, fw_config's population happened before the cache gets
enabled.
Hence to boost the performance, moved fw_config's population
after
plat/arm: Move fconf population after the enablement of MMU
In BL2, fw_config's population happened before the cache gets
enabled.
Hence to boost the performance, moved fw_config's population
after cache gets enabled (i.e. after MMU gets enabled).
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2e75cabd76b1cb7a660f6b72f409ab40d2877284
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|
| f4417189 | 15-Jul-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
lib/fconf: Update 'set_fw_config_info' function
Updated the function 'set_fw_config_info' to make it generic
by doing below changes:
1. Rename function name from 'set_fw_config_info' to 'set_config
lib/fconf: Update 'set_fw_config_info' function
Updated the function 'set_fw_config_info' to make it generic
by doing below changes:
1. Rename function name from 'set_fw_config_info' to 'set_config_info'
2. Take image_id as an argument so that this function can set any
config information.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Icf29e19d3e9996d8154d84dbbbc76712fab0f0c1
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|
| a4ff9d7e | 15-Jul-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
lib/fconf: Update data type of config max size
Update the data type of the member 'config_max_size' present in the
structure 'dyn_cfg_dtb_info_t' to uint32_t.
This change is being done so that dyn_
lib/fconf: Update data type of config max size
Update the data type of the member 'config_max_size' present in the
structure 'dyn_cfg_dtb_info_t' to uint32_t.
This change is being done so that dyn_cfg_dtb_info_t and image_info
structure should use same data type for maximum size.
Change-Id: I9b5927a47eb8351bbf3664b8b1e047ae1ae5a260
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 3ee148d6 | 22-Jul-2020 |
joanna.farley <joanna.farley@arm.com> |
Merge changes from topics "af/add_measured_boot_bl1_bl2", "af/add_measured_boot_driver", "af/add_measured_boot_driver_support", "af/add_measured_boot_fconf", "af/add_measured_boot_fvp" into integrati
Merge changes from topics "af/add_measured_boot_bl1_bl2", "af/add_measured_boot_driver", "af/add_measured_boot_driver_support", "af/add_measured_boot_fconf", "af/add_measured_boot_fvp" into integration
* changes:
plat/arm/board/fvp: Add support for Measured Boot
TF-A: Add support for Measured Boot driver to FCONF
TF-A: Add support for Measured Boot driver in BL1 and BL2
TF-A: Add Event Log for Measured Boot
TF-A: Add support for Measured Boot driver
show more ...
|
| 43f7d887 | 22-Jul-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "stm32-scmi" into integration
* changes:
stm32mp1: SCMI clock and reset service in SP_MIN
dts: bindings: stm32mp1: define SCMI clock and reset domain IDs |
| d686fa3b | 13-Jul-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Add Event Log for Measured Boot
This patch adds support for Event Log generation required
for Measured Boot functionality.
Change-Id: I34f05a33565e6659e78499d62cc6fb00b7d6c2dc
Signed-off-by:
TF-A: Add Event Log for Measured Boot
This patch adds support for Event Log generation required
for Measured Boot functionality.
Change-Id: I34f05a33565e6659e78499d62cc6fb00b7d6c2dc
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
show more ...
|
| 7b4e1fbb | 13-Jul-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Add support for Measured Boot driver
This patch adds support for Measured Boot driver functionality
in common Arm platform code.
Change-Id: If049dcf8d847c39023b77c0d805a8cf5b8bcaa3e
Signed-of
TF-A: Add support for Measured Boot driver
This patch adds support for Measured Boot driver functionality
in common Arm platform code.
Change-Id: If049dcf8d847c39023b77c0d805a8cf5b8bcaa3e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| 70501930 | 20-Jul-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "TF-A: Redefine true/false definitions" into integration |
| 5a430c02 | 09-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
rpi4/fdt: Move dtb_size() function to fdt_wrappers.h
Getting the actual size of a DTB blob is useful beyond the Raspberry Pi
port, so let's move this helper to a common header.
Change-Id: Ia5be46e9
rpi4/fdt: Move dtb_size() function to fdt_wrappers.h
Getting the actual size of a DTB blob is useful beyond the Raspberry Pi
port, so let's move this helper to a common header.
Change-Id: Ia5be46e9353ca859a1e5ad9e3c057a322dfe22e2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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|