1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 11 #define PLAT_PRIMARY_CPU 0x0 12 13 #define MT_GIC_BASE 0x0c000000 14 #define PLAT_MT_CCI_BASE 0x0c500000 15 #define MCUCFG_BASE 0x0c530000 16 17 #define IO_PHYS 0x10000000 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE IO_PHYS 21 #define MTK_DEV_RNG0_SIZE 0x10000000 22 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000) 23 #define MTK_DEV_RNG1_SIZE 0x10000000 24 #define MTK_DEV_RNG2_BASE 0x0c000000 25 #define MTK_DEV_RNG2_SIZE 0x600000 26 27 /******************************************************************************* 28 * UART related constants 29 ******************************************************************************/ 30 #define UART0_BASE (IO_PHYS + 0x01002000) 31 #define UART1_BASE (IO_PHYS + 0x01003000) 32 33 #define UART_BAUDRATE 115200 34 35 /******************************************************************************* 36 * System counter frequency related constants 37 ******************************************************************************/ 38 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 39 #define SYS_COUNTER_FREQ_IN_MHZ 13 40 41 /******************************************************************************* 42 * GIC-400 & interrupt handling related constants 43 ******************************************************************************/ 44 45 /* Base MTK_platform compatible GIC memory map */ 46 #define BASE_GICD_BASE MT_GIC_BASE 47 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 48 49 /******************************************************************************* 50 * Platform binary types for linking 51 ******************************************************************************/ 52 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 53 #define PLATFORM_LINKER_ARCH aarch64 54 55 /******************************************************************************* 56 * Generic platform constants 57 ******************************************************************************/ 58 #define PLATFORM_STACK_SIZE 0x800 59 60 #define PLAT_MAX_PWR_LVL U(2) 61 #define PLAT_MAX_RET_STATE U(1) 62 #define PLAT_MAX_OFF_STATE U(2) 63 64 #define PLATFORM_SYSTEM_COUNT U(1) 65 #define PLATFORM_CLUSTER_COUNT U(1) 66 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 67 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 68 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 69 70 #define SOC_CHIP_ID U(0x8192) 71 72 /******************************************************************************* 73 * Platform memory map related constants 74 ******************************************************************************/ 75 #define TZRAM_BASE 0x54600000 76 #define TZRAM_SIZE 0x00030000 77 78 /******************************************************************************* 79 * BL31 specific defines. 80 ******************************************************************************/ 81 /* 82 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 83 * present). BL31_BASE is calculated using the current BL31 debug size plus a 84 * little space for growth. 85 */ 86 #define BL31_BASE (TZRAM_BASE + 0x1000) 87 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 88 89 /******************************************************************************* 90 * Platform specific page table and MMU setup constants 91 ******************************************************************************/ 92 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 93 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 94 #define MAX_XLAT_TABLES 16 95 #define MAX_MMAP_REGIONS 16 96 97 /******************************************************************************* 98 * Declarations and constants to access the mailboxes safely. Each mailbox is 99 * aligned on the biggest cache line size in the platform. This is known only 100 * to the platform as it might have a combination of integrated and external 101 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 102 * line at any cache level. They could belong to different cpus/clusters & 103 * get written while being protected by different locks causing corruption of 104 * a valid mailbox address. 105 ******************************************************************************/ 106 #define CACHE_WRITEBACK_SHIFT 6 107 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 108 #endif /* PLATFORM_DEF_H */ 109