1# 2# Copyright (c) 2016-2020, ARM Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture major and minor versions: 8.0 by default. 23ARM_ARCH_MAJOR := 8 24ARM_ARCH_MINOR := 0 25 26# Base commit to perform code check on 27BASE_COMMIT := origin/master 28 29# Execute BL2 at EL3 30BL2_AT_EL3 := 0 31 32# BL2 image is stored in XIP memory, for now, this option is only supported 33# when BL2_AT_EL3 is 1. 34BL2_IN_XIP_MEM := 0 35 36# Do dcache invalidate upon BL2 entry at EL3 37BL2_INV_DCACHE := 1 38 39# Select the branch protection features to use. 40BRANCH_PROTECTION := 0 41 42# By default, consider that the platform may release several CPUs out of reset. 43# The platform Makefile is free to override this value. 44COLD_BOOT_SINGLE_CPU := 0 45 46# Flag to compile in coreboot support code. Exclude by default. The coreboot 47# Makefile system will set this when compiling TF as part of a coreboot image. 48COREBOOT := 0 49 50# For Chain of Trust 51CREATE_KEYS := 1 52 53# Build flag to include AArch32 registers in cpu context save and restore during 54# world switch. This flag must be set to 0 for AArch64-only platforms. 55CTX_INCLUDE_AARCH32_REGS := 1 56 57# Include FP registers in cpu context 58CTX_INCLUDE_FPREGS := 0 59 60# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 61# must be set to 1 if the platform wants to use this feature in the Secure 62# world. It is not needed to use it in the Non-secure world. 63CTX_INCLUDE_PAUTH_REGS := 0 64 65# Include Nested virtualization control (Armv8.4-NV) registers in cpu context. 66# This must be set to 1 if architecture implements Nested Virtualization 67# Extension and platform wants to use this feature in the Secure world 68CTX_INCLUDE_NEVE_REGS := 0 69 70# Debug build 71DEBUG := 0 72 73# By default disable authenticated decryption support. 74DECRYPTION_SUPPORT := none 75 76# Build platform 77DEFAULT_PLAT := fvp 78 79# Disable the generation of the binary image (ELF only). 80DISABLE_BIN_GENERATION := 0 81 82# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards 83# compatibility. 84DISABLE_MTPMU := 0 85 86# Enable capability to disable authentication dynamically. Only meant for 87# development platforms. 88DYN_DISABLE_AUTH := 0 89 90# Build option to enable MPAM for lower ELs 91ENABLE_MPAM_FOR_LOWER_ELS := 0 92 93# Flag to Enable Position Independant support (PIE) 94ENABLE_PIE := 0 95 96# Flag to enable Performance Measurement Framework 97ENABLE_PMF := 0 98 99# Flag to enable PSCI STATs functionality 100ENABLE_PSCI_STAT := 0 101 102# Flag to enable runtime instrumentation using PMF 103ENABLE_RUNTIME_INSTRUMENTATION := 0 104 105# Flag to enable stack corruption protection 106ENABLE_STACK_PROTECTOR := 0 107 108# Flag to enable exception handling in EL3 109EL3_EXCEPTION_HANDLING := 0 110 111# Flag to enable Branch Target Identification. 112# Internal flag not meant for direct setting. 113# Use BRANCH_PROTECTION to enable BTI. 114ENABLE_BTI := 0 115 116# Flag to enable Pointer Authentication. 117# Internal flag not meant for direct setting. 118# Use BRANCH_PROTECTION to enable PAUTH. 119ENABLE_PAUTH := 0 120 121# By default BL31 encryption disabled 122ENCRYPT_BL31 := 0 123 124# By default BL32 encryption disabled 125ENCRYPT_BL32 := 0 126 127# Default dummy firmware encryption key 128ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 129 130# Default dummy nonce for firmware encryption 131ENC_NONCE := 1234567890abcdef12345678 132 133# Build flag to treat usage of deprecated platform and framework APIs as error. 134ERROR_DEPRECATED := 0 135 136# Fault injection support 137FAULT_INJECTION_SUPPORT := 0 138 139# Byte alignment that each component in FIP is aligned to 140FIP_ALIGN := 0 141 142# Default FIP file name 143FIP_NAME := fip.bin 144 145# Default FWU_FIP file name 146FWU_FIP_NAME := fwu_fip.bin 147 148# By default firmware encryption with SSK 149FW_ENC_STATUS := 0 150 151# For Chain of Trust 152GENERATE_COT := 0 153 154# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 155# default, they are for Secure EL1. 156GICV2_G0_FOR_EL3 := 0 157 158# Route External Aborts to EL3. Disabled by default; External Aborts are handled 159# by lower ELs. 160HANDLE_EA_EL3_FIRST := 0 161 162# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 163# The default value is sha256. 164HASH_ALG := sha256 165 166# Whether system coherency is managed in hardware, without explicit software 167# operations. 168HW_ASSISTED_COHERENCY := 0 169 170# Set the default algorithm for the generation of Trusted Board Boot keys 171KEY_ALG := rsa 172 173# Set the default key size in case KEY_ALG is rsa 174ifeq ($(KEY_ALG),rsa) 175KEY_SIZE := 2048 176endif 177 178# Option to build TF with Measured Boot support 179MEASURED_BOOT := 0 180 181# NS timer register save and restore 182NS_TIMER_SWITCH := 0 183 184# Include lib/libc in the final image 185OVERRIDE_LIBC := 0 186 187# Build PL011 UART driver in minimal generic UART mode 188PL011_GENERIC_UART := 0 189 190# By default, consider that the platform's reset address is not programmable. 191# The platform Makefile is free to override this value. 192PROGRAMMABLE_RESET_ADDRESS := 0 193 194# Flag used to choose the power state format: Extended State-ID or Original 195PSCI_EXTENDED_STATE_ID := 0 196 197# Enable RAS support 198RAS_EXTENSION := 0 199 200# By default, BL1 acts as the reset handler, not BL31 201RESET_TO_BL31 := 0 202 203# For Chain of Trust 204SAVE_KEYS := 0 205 206# Software Delegated Exception support 207SDEI_SUPPORT := 0 208 209# Whether code and read-only data should be put on separate memory pages. The 210# platform Makefile is free to override this value. 211SEPARATE_CODE_AND_RODATA := 0 212 213# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 214# separate memory region, which may be discontiguous from the rest of BL31. 215SEPARATE_NOBITS_REGION := 0 216 217# If the BL31 image initialisation code is recalimed after use for the secondary 218# cores stack 219RECLAIM_INIT_CODE := 0 220 221# SPD choice 222SPD := none 223 224# Enable the Management Mode (MM)-based Secure Partition Manager implementation 225SPM_MM := 0 226 227# Use SPM at S-EL2 as a default config for SPMD 228SPMD_SPM_AT_SEL2 := 1 229 230# Flag to introduce an infinite loop in BL1 just before it exits into the next 231# image. This is meant to help debugging the post-BL2 phase. 232SPIN_ON_BL1_EXIT := 0 233 234# Flags to build TF with Trusted Boot support 235TRUSTED_BOARD_BOOT := 0 236 237# Build option to choose whether Trusted Firmware uses Coherent memory or not. 238USE_COHERENT_MEM := 1 239 240# Build option to add debugfs support 241USE_DEBUGFS := 0 242 243# Build option to fconf based io 244ARM_IO_IN_DTB := 0 245 246# Build option to support SDEI through fconf 247SDEI_IN_FCONF := 0 248 249# Build option to support Secure Interrupt descriptors through fconf 250SEC_INT_DESC_IN_FCONF := 0 251 252# Build option to choose whether Trusted Firmware uses library at ROM 253USE_ROMLIB := 0 254 255# Build option to choose whether the xlat tables of BL images can be read-only. 256# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 257# which is the per BL-image option that actually enables the read-only tables 258# API. The reason for having this additional option is to have a common high 259# level makefile where we can check for incompatible features/build options. 260ALLOW_RO_XLAT_TABLES := 0 261 262# Chain of trust. 263COT := tbbr 264 265# Use tbbr_oid.h instead of platform_oid.h 266USE_TBBR_DEFS := 1 267 268# Build verbosity 269V := 0 270 271# Whether to enable D-Cache early during warm boot. This is usually 272# applicable for platforms wherein interconnect programming is not 273# required to enable cache coherency after warm reset (eg: single cluster 274# platforms). 275WARMBOOT_ENABLE_DCACHE_EARLY := 0 276 277# Build option to enable/disable the Statistical Profiling Extensions 278ENABLE_SPE_FOR_LOWER_ELS := 1 279 280# SPE is only supported on AArch64 so disable it on AArch32. 281ifeq (${ARCH},aarch32) 282 override ENABLE_SPE_FOR_LOWER_ELS := 0 283endif 284 285# Include Memory Tagging Extension registers in cpu context. This must be set 286# to 1 if the platform wants to use this feature in the Secure world and MTE is 287# enabled at ELX. 288CTX_INCLUDE_MTE_REGS := 0 289 290ENABLE_AMU := 0 291 292# By default, enable Scalable Vector Extension if implemented for Non-secure 293# lower ELs 294# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 295ifneq (${ARCH},aarch32) 296 ENABLE_SVE_FOR_NS := 1 297else 298 override ENABLE_SVE_FOR_NS := 0 299endif 300 301SANITIZE_UB := off 302 303# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 304# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 305# Default: disabled 306USE_SPINLOCK_CAS := 0 307 308# Enable Link Time Optimization 309ENABLE_LTO := 0 310 311# Build flag to include EL2 registers in cpu context save and restore during 312# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option. 313# Default is 0. 314CTX_INCLUDE_EL2_REGS := 0 315 316# Enable Memory tag extension which is supported for architecture greater 317# than Armv8.5-A 318# By default it is set to "no" 319SUPPORT_STACK_MEMTAG := no 320 321# Select workaround for AT speculative behaviour. 322ERRATA_SPECULATIVE_AT := 0 323 324# Trap RAS error record access from lower EL 325RAS_TRAP_LOWER_EL_ERR_ACCESS := 0 326 327# Build option to create cot descriptors using fconf 328COT_DESC_IN_DTB := 0 329 330# Build option to provide openssl directory path 331OPENSSL_DIR := /usr 332 333# Build option to use the SP804 timer instead of the generic one 334USE_SP804_TIMER := 0 335