1 /* 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A77_H 8 #define CORTEX_A77_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A77 MIDR */ 13 #define CORTEX_A77_MIDR U(0x410FD0D0) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions. 17 ******************************************************************************/ 18 #define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 19 #define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) 20 #define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) 21 22 /******************************************************************************* 23 * CPU Power Control register specific definitions. 24 ******************************************************************************/ 25 #define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 26 #define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) 27 28 #define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 29 #define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 30 #define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2 31 #define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3 32 #define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4 33 #define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5 34 35 #endif /* CORTEX_A77_H */ 36