1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 26 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 27 ``aarch64``. 28 29- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 30 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 31 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 32 :ref:`Firmware Design`. 33 34- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 35 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 36 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 37 38- ``BL2``: This is an optional build option which specifies the path to BL2 39 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 40 built. 41 42- ``BL2U``: This is an optional build option which specifies the path to 43 BL2U image. In this case, the BL2U in TF-A will not be built. 44 45- ``BL2_AT_EL3``: This is an optional build option that enables the use of 46 BL2 at EL3 execution level. 47 48- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 49 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 50 the RW sections in RAM, while leaving the RO sections in place. This option 51 enable this use-case. For now, this option is only supported when BL2_AT_EL3 52 is set to '1'. 53 54- ``BL31``: This is an optional build option which specifies the path to 55 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 56 be built. 57 58- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 59 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 60 this file name will be used to save the key. 61 62- ``BL32``: This is an optional build option which specifies the path to 63 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 64 be built. 65 66- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 67 Trusted OS Extra1 image for the ``fip`` target. 68 69- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 70 Trusted OS Extra2 image for the ``fip`` target. 71 72- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 73 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 74 this file name will be used to save the key. 75 76- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 77 ``fip`` target in case TF-A BL2 is used. 78 79- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 80 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 81 this file name will be used to save the key. 82 83- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 84 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 85 If enabled, it is needed to use a compiler that supports the option 86 ``-mbranch-protection``. Selects the branch protection features to use: 87- 0: Default value turns off all types of branch protection 88- 1: Enables all types of branch protection features 89- 2: Return address signing to its standard level 90- 3: Extend the signing to include leaf functions 91- 4: Turn on branch target identification mechanism 92 93 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 94 and resulting PAuth/BTI features. 95 96 +-------+--------------+-------+-----+ 97 | Value | GCC option | PAuth | BTI | 98 +=======+==============+=======+=====+ 99 | 0 | none | N | N | 100 +-------+--------------+-------+-----+ 101 | 1 | standard | Y | Y | 102 +-------+--------------+-------+-----+ 103 | 2 | pac-ret | Y | N | 104 +-------+--------------+-------+-----+ 105 | 3 | pac-ret+leaf | Y | N | 106 +-------+--------------+-------+-----+ 107 | 4 | bti | N | Y | 108 +-------+--------------+-------+-----+ 109 110 This option defaults to 0 and this is an experimental feature. 111 Note that Pointer Authentication is enabled for Non-secure world 112 irrespective of the value of this option if the CPU supports it. 113 114- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 115 compilation of each build. It must be set to a C string (including quotes 116 where applicable). Defaults to a string that contains the time and date of 117 the compilation. 118 119- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 120 build to be uniquely identified. Defaults to the current git commit id. 121 122- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 123 124- ``CFLAGS``: Extra user options appended on the compiler's command line in 125 addition to the options set by the build system. 126 127- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 128 release several CPUs out of reset. It can take either 0 (several CPUs may be 129 brought up) or 1 (only one CPU will ever be brought up during cold reset). 130 Default is 0. If the platform always brings up a single CPU, there is no 131 need to distinguish between primary and secondary CPUs and the boot path can 132 be optimised. The ``plat_is_my_cpu_primary()`` and 133 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 134 to be implemented in this case. 135 136- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 137 Defaults to ``tbbr``. 138 139- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 140 register state when an unexpected exception occurs during execution of 141 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 142 this is only enabled for a debug build of the firmware. 143 144- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 145 certificate generation tool to create new keys in case no valid keys are 146 present or specified. Allowed options are '0' or '1'. Default is '1'. 147 148- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 149 the AArch32 system registers to be included when saving and restoring the 150 CPU context. The option must be set to 0 for AArch64-only platforms (that 151 is on hardware that does not implement AArch32, or at least not at EL1 and 152 higher ELs). Default value is 1. 153 154- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore 155 operations when entering/exiting an EL2 execution context. This is of primary 156 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). 157 This option must be equal to 1 (enabled) when ``SPD=spmd`` and 158 ``SPMD_SPM_AT_SEL2`` is set. 159 160- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 161 registers to be included when saving and restoring the CPU context. Default 162 is 0. 163 164- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the 165 Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 166 execution context. Default value is 0. 167 168- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables 169 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth 170 registers to be included when saving and restoring the CPU context as 171 part of world switch. Default value is 0 and this is an experimental feature. 172 Note that Pointer Authentication is enabled for Non-secure world irrespective 173 of the value of this flag if the CPU supports it. 174 175- ``DEBUG``: Chooses between a debug and release build. It can take either 0 176 (release) or 1 (debug) as values. 0 is the default. 177 178- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 179 authenticated decryption algorithm to be used to decrypt firmware/s during 180 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 181 this flag is ``none`` to disable firmware decryption which is an optional 182 feature as per TBBR. Also, it is an experimental feature. 183 184- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 185 of the binary image. If set to 1, then only the ELF image is built. 186 0 is the default. 187 188- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 189 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 190 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 191 check the latest Arm ARM. 192 193- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 194 Board Boot authentication at runtime. This option is meant to be enabled only 195 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 196 flag has to be enabled. 0 is the default. 197 198- ``E``: Boolean option to make warnings into errors. Default is 1. 199 200- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 201 the normal boot flow. It must specify the entry point address of the EL3 202 payload. Please refer to the "Booting an EL3 payload" section for more 203 details. 204 205- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 206 This is an optional architectural feature available on v8.4 onwards. Some 207 v8.2 implementations also implement an AMU and this option can be used to 208 enable this feature on those systems as well. Default is 0. 209 210- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 211 are compiled out. For debug builds, this option defaults to 1, and calls to 212 ``assert()`` are left in place. For release builds, this option defaults to 0 213 and calls to ``assert()`` function are compiled out. This option can be set 214 independently of ``DEBUG``. It can also be used to hide any auxiliary code 215 that is only required for the assertion and does not fit in the assertion 216 itself. 217 218- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 219 dumps or not. It is supported in both AArch64 and AArch32. However, in 220 AArch32 the format of the frame records are not defined in the AAPCS and they 221 are defined by the implementation. This implementation of backtrace only 222 supports the format used by GCC when T32 interworking is disabled. For this 223 reason enabling this option in AArch32 will force the compiler to only 224 generate A32 code. This option is enabled by default only in AArch64 debug 225 builds, but this behaviour can be overridden in each platform's Makefile or 226 in the build command line. 227 228- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 229 support in GCC for TF-A. This option is currently only supported for 230 AArch64. Default is 0. 231 232- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM 233 feature. MPAM is an optional Armv8.4 extension that enables various memory 234 system components and resources to define partitions; software running at 235 various ELs can assign themselves to desired partition to control their 236 performance aspects. 237 238 When this option is set to ``1``, EL3 allows lower ELs to access their own 239 MPAM registers without trapping into EL3. This option doesn't make use of 240 partitioning in EL3, however. Platform initialisation code should configure 241 and use partitions in EL3 as required. This option defaults to ``0``. 242 243- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 244 support within generic code in TF-A. This option is currently only supported 245 in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0. 246 247- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 248 Measurement Framework(PMF). Default is 0. 249 250- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 251 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 252 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 253 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 254 software. 255 256- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 257 instrumentation which injects timestamp collection points into TF-A to 258 allow runtime performance to be measured. Currently, only PSCI is 259 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 260 as well. Default is 0. 261 262- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 263 extensions. This is an optional architectural feature for AArch64. 264 The default is 1 but is automatically disabled when the target architecture 265 is AArch32. 266 267- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 268 (SVE) for the Non-secure world only. SVE is an optional architectural feature 269 for AArch64. Note that when SVE is enabled for the Non-secure world, access 270 to SIMD and floating-point functionality from the Secure world is disabled. 271 This is to avoid corruption of the Non-secure world data in the Z-registers 272 which are aliased by the SIMD and FP registers. The build option is not 273 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 274 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 275 1. The default is 1 but is automatically disabled when the target 276 architecture is AArch32. 277 278- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 279 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 280 default value is set to "none". "strong" is the recommended stack protection 281 level if this feature is desired. "none" disables the stack protection. For 282 all values other than "none", the ``plat_get_stack_protector_canary()`` 283 platform hook needs to be implemented. The value is passed as the last 284 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 285 286- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 287 flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 288 experimental. 289 290- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 291 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 292 experimental. 293 294- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 295 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 296 on ``DECRYPTION_SUPPORT`` build flag which is marked as experimental. 297 298- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 299 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 300 build flag which is marked as experimental. 301 302- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 303 deprecated platform APIs, helper functions or drivers within Trusted 304 Firmware as error. It can take the value 1 (flag the use of deprecated 305 APIs as error) or 0. The default is 0. 306 307- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 308 targeted at EL3. When set ``0`` (default), no exceptions are expected or 309 handled at EL3, and a panic will result. This is supported only for AArch64 310 builds. 311 312- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 313 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 314 Default value is 40 (LOG_LEVEL_INFO). 315 316- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 317 injection from lower ELs, and this build option enables lower ELs to use 318 Error Records accessed via System Registers to inject faults. This is 319 applicable only to AArch64 builds. 320 321 This feature is intended for testing purposes only, and is advisable to keep 322 disabled for production images. 323 324- ``FIP_NAME``: This is an optional build option which specifies the FIP 325 filename for the ``fip`` target. Default is ``fip.bin``. 326 327- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 328 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 329 330- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 331 332 :: 333 334 0: Encryption is done with Secret Symmetric Key (SSK) which is common 335 for a class of devices. 336 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 337 unique per device. 338 339 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 340 experimental. 341 342- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 343 tool to create certificates as per the Chain of Trust described in 344 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 345 include the certificates in the FIP and FWU_FIP. Default value is '0'. 346 347 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 348 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 349 the corresponding certificates, and to include those certificates in the 350 FIP and FWU_FIP. 351 352 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 353 images will not include support for Trusted Board Boot. The FIP will still 354 include the corresponding certificates. This FIP can be used to verify the 355 Chain of Trust on the host machine through other mechanisms. 356 357 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 358 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 359 will not include the corresponding certificates, causing a boot failure. 360 361- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 362 inherent support for specific EL3 type interrupts. Setting this build option 363 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 364 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 365 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 366 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 367 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 368 the Secure Payload interrupts needs to be synchronously handed over to Secure 369 EL1 for handling. The default value of this option is ``0``, which means the 370 Group 0 interrupts are assumed to be handled by Secure EL1. 371 372- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 373 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 374 ``0`` (default), these exceptions will be trapped in the current exception 375 level (or in EL1 if the current exception level is EL0). 376 377- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 378 software operations are required for CPUs to enter and exit coherency. 379 However, newer systems exist where CPUs' entry to and exit from coherency 380 is managed in hardware. Such systems require software to only initiate these 381 operations, and the rest is managed in hardware, minimizing active software 382 management. In such systems, this boolean option enables TF-A to carry out 383 build and run-time optimizations during boot and power management operations. 384 This option defaults to 0 and if it is enabled, then it implies 385 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 386 387 If this flag is disabled while the platform which TF-A is compiled for 388 includes cores that manage coherency in hardware, then a compilation error is 389 generated. This is based on the fact that a system cannot have, at the same 390 time, cores that manage coherency in hardware and cores that don't. In other 391 words, a platform cannot have, at the same time, cores that require 392 ``HW_ASSISTED_COHERENCY=1`` and cores that require 393 ``HW_ASSISTED_COHERENCY=0``. 394 395 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 396 translation library (xlat tables v2) must be used; version 1 of translation 397 library is not supported. 398 399- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 400 bottom, higher addresses at the top. This buid flag can be set to '1' to 401 invert this behavior. Lower addresses will be printed at the top and higher 402 addresses at the bottom. 403 404- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 405 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 406 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 407 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 408 images. 409 410- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 411 used for generating the PKCS keys and subsequent signing of the certificate. 412 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 413 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 414 compliant and is retained only for compatibility. The default value of this 415 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 416 417- ``KEY_SIZE``: This build flag enables the user to select the key size for 418 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 419 depend on the chosen algorithm and the cryptographic module. 420 421 +-----------+------------------------------------+ 422 | KEY_ALG | Possible key sizes | 423 +===========+====================================+ 424 | rsa | 1024 , 2048 (default), 3072, 4096* | 425 +-----------+------------------------------------+ 426 | ecdsa | unavailable | 427 +-----------+------------------------------------+ 428 429 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 430 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 431 432- ``HASH_ALG``: This build flag enables the user to select the secure hash 433 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 434 The default value of this flag is ``sha256``. 435 436- ``LDFLAGS``: Extra user options appended to the linkers' command line in 437 addition to the one set by the build system. 438 439- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 440 output compiled into the build. This should be one of the following: 441 442 :: 443 444 0 (LOG_LEVEL_NONE) 445 10 (LOG_LEVEL_ERROR) 446 20 (LOG_LEVEL_NOTICE) 447 30 (LOG_LEVEL_WARNING) 448 40 (LOG_LEVEL_INFO) 449 50 (LOG_LEVEL_VERBOSE) 450 451 All log output up to and including the selected log level is compiled into 452 the build. The default value is 40 in debug builds and 20 in release builds. 453 454- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 455 feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set. 456 This option defaults to 0 and is an experimental feature in the stage of 457 development. 458 459- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 460 specifies the file that contains the Non-Trusted World private key in PEM 461 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 462 463- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 464 optional. It is only needed if the platform makefile specifies that it 465 is required in order to build the ``fwu_fip`` target. 466 467- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 468 contents upon world switch. It can take either 0 (don't save and restore) or 469 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 470 wants the timer registers to be saved and restored. 471 472- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 473 for the BL image. It can be either 0 (include) or 1 (remove). The default 474 value is 0. 475 476- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 477 the underlying hardware is not a full PL011 UART but a minimally compliant 478 generic UART, which is a subset of the PL011. The driver will not access 479 any register that is not part of the SBSA generic UART specification. 480 Default value is 0 (a full PL011 compliant UART is present). 481 482- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 483 must be subdirectory of any depth under ``plat/``, and must contain a 484 platform makefile named ``platform.mk``. For example, to build TF-A for the 485 Arm Juno board, select PLAT=juno. 486 487- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 488 instead of the normal boot flow. When defined, it must specify the entry 489 point address for the preloaded BL33 image. This option is incompatible with 490 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 491 over ``PRELOADED_BL33_BASE``. 492 493- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 494 vector address can be programmed or is fixed on the platform. It can take 495 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 496 programmable reset address, it is expected that a CPU will start executing 497 code directly at the right address, both on a cold and warm reset. In this 498 case, there is no need to identify the entrypoint on boot and the boot path 499 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 500 does not need to be implemented in this case. 501 502- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 503 possible for the PSCI power-state parameter: original and extended State-ID 504 formats. This flag if set to 1, configures the generic PSCI layer to use the 505 extended format. The default value of this flag is 0, which means by default 506 the original power-state format is used by the PSCI implementation. This flag 507 should be specified by the platform makefile and it governs the return value 508 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 509 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 510 set to 1 as well. 511 512- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features 513 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 514 or later CPUs. 515 516 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 517 set to ``1``. 518 519 This option is disabled by default. 520 521- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 522 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 523 entrypoint) or 1 (CPU reset to BL31 entrypoint). 524 The default value is 0. 525 526- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 527 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 528 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 529 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 530 531- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 532 file that contains the ROT private key in PEM format and enforces public key 533 hash generation. If ``SAVE_KEYS=1``, this 534 file name will be used to save the key. 535 536- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 537 certificate generation tool to save the keys used to establish the Chain of 538 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 539 540- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 541 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 542 target. 543 544- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 545 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 546 this file name will be used to save the key. 547 548- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 549 optional. It is only needed if the platform makefile specifies that it 550 is required in order to build the ``fwu_fip`` target. 551 552- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 553 Delegated Exception Interface to BL31 image. This defaults to ``0``. 554 555 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 556 set to ``1``. 557 558- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 559 isolated on separate memory pages. This is a trade-off between security and 560 memory usage. See "Isolating code and read-only data on separate memory 561 pages" section in :ref:`Firmware Design`. This flag is disabled by default 562 and affects all BL images. 563 564- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 565 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 566 allocated in RAM discontiguous from the loaded firmware image. When set, the 567 platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and 568 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 569 sections are placed in RAM immediately following the loaded firmware image. 570 571- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 572 This build option is only valid if ``ARCH=aarch64``. The value should be 573 the path to the directory containing the SPD source, relative to 574 ``services/spd/``; the directory is expected to contain a makefile called 575 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 576 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 577 cannot be enabled when the ``SPM_MM`` option is enabled. 578 579- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 580 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 581 execution in BL1 just before handing over to BL31. At this point, all 582 firmware images have been loaded in memory, and the MMU and caches are 583 turned off. Refer to the "Debugging options" section for more details. 584 585- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM 586 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 587 component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 588 extension. This is the default when enabling the SPM Dispatcher. When 589 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 590 state. This latter configuration supports pre-Armv8.4 platforms (aka not 591 implementing the Armv8.4-SecEL2 extension). 592 593- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 594 Partition Manager (SPM) implementation. The default value is ``0`` 595 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 596 enabled (``SPD=spmd``). 597 598- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 599 description of secure partitions. The build system will parse this file and 600 package all secure partition blobs into the FIP. This file is not 601 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 602 603- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 604 secure interrupts (caught through the FIQ line). Platforms can enable 605 this directive if they need to handle such interruption. When enabled, 606 the FIQ are handled in monitor mode and non secure world is not allowed 607 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 608 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 609 610- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 611 Boot feature. When set to '1', BL1 and BL2 images include support to load 612 and verify the certificates and images in a FIP, and BL1 includes support 613 for the Firmware Update. The default value is '0'. Generation and inclusion 614 of certificates in the FIP and FWU_FIP depends upon the value of the 615 ``GENERATE_COT`` option. 616 617 .. warning:: 618 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 619 already exist in disk, they will be overwritten without further notice. 620 621- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 622 specifies the file that contains the Trusted World private key in PEM 623 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 624 625- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 626 synchronous, (see "Initializing a BL32 Image" section in 627 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 628 synchronous method) or 1 (BL32 is initialized using asynchronous method). 629 Default is 0. 630 631- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 632 routing model which routes non-secure interrupts asynchronously from TSP 633 to EL3 causing immediate preemption of TSP. The EL3 is responsible 634 for saving and restoring the TSP context in this routing model. The 635 default routing model (when the value is 0) is to route non-secure 636 interrupts to TSP allowing it to save its context and hand over 637 synchronously to EL3 via an SMC. 638 639 .. note:: 640 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 641 must also be set to ``1``. 642 643- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 644 linker. When the ``LINKER`` build variable points to the armlink linker, 645 this flag is enabled automatically. To enable support for armlink, platforms 646 will have to provide a scatter file for the BL image. Currently, Tegra 647 platforms use the armlink support to compile BL3-1 images. 648 649- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 650 memory region in the BL memory map or not (see "Use of Coherent memory in 651 TF-A" section in :ref:`Firmware Design`). It can take the value 1 652 (Coherent memory region is included) or 0 (Coherent memory region is 653 excluded). Default is 1. 654 655- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 656 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 657 Default is 0. 658 659- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 660 firmware configuration framework. This will move the io_policies into a 661 configuration device tree, instead of static structure in the code base. 662 This is currently an experimental feature. 663 664- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 665 at runtime using fconf. If this flag is enabled, COT descriptors are 666 statically captured in tb_fw_config file in the form of device tree nodes 667 and properties. Currently, COT descriptors used by BL2 are moved to the 668 device tree and COT descriptors used by BL1 are retained in the code 669 base statically. This is currently an experimental feature. 670 671- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 672 runtime using firmware configuration framework. The platform specific SDEI 673 shared and private events configuration is retrieved from device tree rather 674 than static C structures at compile time. This is currently an experimental 675 feature and is only supported if SDEI_SUPPORT build flag is enabled. 676 677- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 678 and Group1 secure interrupts using the firmware configuration framework. The 679 platform specific secure interrupt property descriptor is retrieved from 680 device tree in runtime rather than depending on static C structure at compile 681 time. This is currently an experimental feature. 682 683- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 684 This feature creates a library of functions to be placed in ROM and thus 685 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 686 is 0. 687 688- ``V``: Verbose build. If assigned anything other than 0, the build commands 689 are printed. Default is 0. 690 691- ``VERSION_STRING``: String used in the log output for each TF-A image. 692 Defaults to a string formed by concatenating the version number, build type 693 and build string. 694 695- ``W``: Warning level. Some compiler warning options of interest have been 696 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 697 each level enabling more warning options. Default is 0. 698 699- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 700 the CPU after warm boot. This is applicable for platforms which do not 701 require interconnect programming to enable cache coherency (eg: single 702 cluster platforms). If this option is enabled, then warm boot path 703 enables D-caches immediately after enabling MMU. This option defaults to 0. 704 705- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 706 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 707 default value of this flag is ``no``. Note this option must be enabled only 708 for ARM architecture greater than Armv8.5-A. 709 710- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 711 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 712 The default value of this flag is ``0``. 713 714 ``AT`` speculative errata workaround disables stage1 page table walk for 715 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 716 produces either the correct result or failure without TLB allocation. 717 718 This boolean option enables errata for all below CPUs. 719 720 +---------+--------------+-------------------------+ 721 | Errata | CPU | Workaround Define | 722 +=========+==============+=========================+ 723 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 724 +---------+--------------+-------------------------+ 725 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 726 +---------+--------------+-------------------------+ 727 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 728 +---------+--------------+-------------------------+ 729 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 730 +---------+--------------+-------------------------+ 731 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 732 +---------+--------------+-------------------------+ 733 734 .. note:: 735 This option is enabled by build only if platform sets any of above defines 736 mentioned in ’Workaround Define' column in the table. 737 If this option is enabled for the EL3 software then EL2 software also must 738 implement this workaround due to the behaviour of the errata mentioned 739 in new SDEN document which will get published soon. 740 741- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR 742 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 743 This flag is disabled by default. 744 745- ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory 746 path on the host machine which is used to build certificate generation and 747 firmware encryption tool. 748 749- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 750 functions that wait for an arbitrary time length (udelay and mdelay). The 751 default value is 0. 752 753GICv3 driver options 754-------------------- 755 756GICv3 driver files are included using directive: 757 758``include drivers/arm/gic/v3/gicv3.mk`` 759 760The driver can be configured with the following options set in the platform 761makefile: 762 763- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 764 Enabling this option will add runtime detection support for the 765 GIC-600, so is safe to select even for a GIC500 implementation. 766 This option defaults to 0. 767 768- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 769 functionality. This option defaults to 0 770 771- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 772 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 773 functions. This is required for FVP platform which need to simulate GIC save 774 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 775 776- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 777 This option defaults to 0. 778 779- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 780 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 781 782Debugging options 783----------------- 784 785To compile a debug version and make the build more verbose use 786 787.. code:: shell 788 789 make PLAT=<platform> DEBUG=1 V=1 all 790 791AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 792example DS-5) might not support this and may need an older version of DWARF 793symbols to be emitted by GCC. This can be achieved by using the 794``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 795version to 2 is recommended for DS-5 versions older than 5.16. 796 797When debugging logic problems it might also be useful to disable all compiler 798optimizations by using ``-O0``. 799 800.. warning:: 801 Using ``-O0`` could cause output images to be larger and base addresses 802 might need to be recalculated (see the **Memory layout on Arm development 803 platforms** section in the :ref:`Firmware Design`). 804 805Extra debug options can be passed to the build system by setting ``CFLAGS`` or 806``LDFLAGS``: 807 808.. code:: shell 809 810 CFLAGS='-O0 -gdwarf-2' \ 811 make PLAT=<platform> DEBUG=1 V=1 all 812 813Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 814ignored as the linker is called directly. 815 816It is also possible to introduce an infinite loop to help in debugging the 817post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 818``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 819section. In this case, the developer may take control of the target using a 820debugger when indicated by the console output. When using DS-5, the following 821commands can be used: 822 823:: 824 825 # Stop target execution 826 interrupt 827 828 # 829 # Prepare your debugging environment, e.g. set breakpoints 830 # 831 832 # Jump over the debug loop 833 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 834 835 # Resume execution 836 continue 837 838-------------- 839 840*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* 841