| f2d6b4ee | 24-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal L
Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.
To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
show more ...
|
| 61cbd41d | 15-Jan-2020 |
Andrew Walbran <qwandor@google.com> |
qemu: Implement qemu_system_off via semihosting.
This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.
Sig
qemu: Implement qemu_system_off via semihosting.
This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.
Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03
show more ...
|
| e76d9fc4 | 02-Jan-2020 |
Lionel Debieve <lionel.debieve@st.com> |
lib: utils_def: add CLAMP macro
Add the standard CLAMP macro. It ensures that
x is between the limits set by low and high.
If low is greater than high the result is undefined.
Signed-off-by: Lione
lib: utils_def: add CLAMP macro
Add the standard CLAMP macro. It ensures that
x is between the limits set by low and high.
If low is greater than high the result is undefined.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Ia173bb9ca51bc8d9a8ec573bbc15636a94f881f4
show more ...
|
| 43636796 | 10-Jan-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Unify type of "cpu_idx" across PSCI module." into integration |
| 5b33ad17 | 13-Dec-2019 |
Deepika Bhavnani <deepika.bhavnani@arm.com> |
Unify type of "cpu_idx" across PSCI module.
NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned i
Unify type of "cpu_idx" across PSCI module.
NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned int" type.
Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.
2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent
Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.
Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
show more ...
|
| 45503af4 | 09-Jan-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "smccc: add get smc function id num macro" into integration |
| e073e070 | 23-Dec-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
smccc: add get smc function id num macro
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2953f0a6f35bc678402bc185640d1f328b065af5 |
| daa9b6ea | 06-Jan-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Simplify PMF helper macro definitions across header files
In further patches, we aim to enable -Wredundant-decls by default.
This rearragement of helper macros is necessary to make Coverity
tool hap
Simplify PMF helper macro definitions across header files
In further patches, we aim to enable -Wredundant-decls by default.
This rearragement of helper macros is necessary to make Coverity
tool happy as well as making sure there are no redundant function
declarations for PMF related declarations.
Also, PMF related macros were added to provide appropriate function
declarations for helper APIs which capture PSCI statistics.
Change-Id: I36273032dde8fa079ef71235ed3a4629c5bfd981
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
show more ...
|
| 0348ee49 | 30-Dec-2019 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Workaround for Hercules erratum 1688305" into integration |
| 83e95524 | 18-Dec-2019 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Workaround for Hercules erratum 1688305
Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined
Workaround for Hercules erratum 1688305
Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined register CPUACTLR2_EL1 to 1 to prevent store-
release from being dispatched before it is the oldest.
Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
show more ...
|
| ba4b453b | 12-Apr-2019 |
Sheetal Tigadoli <sheetal.tigadoli@broadcom.com> |
lib: cpu: Add additional field definition for A72 L2 control
Add additional field definitions for
Cortex_A72 L2 Control registers
Change-Id: I5ef3a6db41cd7c5d9904172720682716276b7889
Signed-off-by:
lib: cpu: Add additional field definition for A72 L2 control
Add additional field definitions for
Cortex_A72 L2 Control registers
Change-Id: I5ef3a6db41cd7c5d9904172720682716276b7889
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
show more ...
|
| 86ed8953 | 20-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "debugfs: add SMC channel" into integration |
| be84a5b9 | 20-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "debugfs: add 9p device interface" into integration |
| 538b0020 | 14-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
spm: Remove SPM Alpha 1 prototype and support files
The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component
spm: Remove SPM Alpha 1 prototype and support files
The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component that, in turn, enables partition managers
at S-EL2 / S-EL1.
This patch removes:
- The core service files (std_svc/spm)
- The Resource Descriptor headers (include/services)
- SPRT protocol support and service definitions
- SPCI protocol support and service definitions
Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
show more ...
|
| b8e17967 | 20-Dec-2019 |
György Szing <gyorgy.szing@arm.com> |
Merge changes from topic "bs/pmf32" into integration
* changes:
pmf: Make the runtime instrumentation work on AArch32
SiP: Don't validate entrypoint if state switch is impossible |
| 992f091b | 12-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
debugfs: add SMC channel
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.
Signed-
debugfs: add SMC channel
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9314662314bb060f6bc02714476574da158b2a7d
show more ...
|
| 4e0d14f2 | 17-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "arm: gicv3: Fix compiler dependent behavior" into integration |
| 0531ada5 | 07-Nov-2019 |
Bence Szépkúti <bence.szepkuti@arm.com> |
pmf: Make the runtime instrumentation work on AArch32
Ported the pmf asm macros and the asm code in the bl31 entrypoint
necessary for the instrumentation to AArch32.
Since smc dispatch is handled b
pmf: Make the runtime instrumentation work on AArch32
Ported the pmf asm macros and the asm code in the bl31 entrypoint
necessary for the instrumentation to AArch32.
Since smc dispatch is handled by the bl32 payload on AArch32, we
provide this service only if AARCH32_SP=sp_min is set.
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Id33b7e9762ae86a4f4b40d7f1b37a90e5130c8ac
show more ...
|
| 0ca3913d | 19-Sep-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
debugfs: add 9p device interface
The 9p interface provides abstraction layers allowing the software
that uses devices to be independent from the hardware.
This patch provides a file system abstract
debugfs: add 9p device interface
The 9p interface provides abstraction layers allowing the software
that uses devices to be independent from the hardware.
This patch provides a file system abstraction to link drivers to their
devices and propose a common interface to expose driver operations to
higher layers. This file system can be used to access and configure a
device by doing read/write operations.
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia9662393baf489855dc0c8f389fe4a0afbc9c255
show more ...
|
| ae4a90f2 | 16-Dec-2019 |
Bence Szépkúti <bence.szepkuti@arm.com> |
libc: Fix SIZE_MAX on AArch32
SIZE_MAX was mistakenly redefined from UINT32_MAX to UINT64_MAX
on AArch32 when the arch-specific headers were merged.
This value is not currently used by upstream TF-
libc: Fix SIZE_MAX on AArch32
SIZE_MAX was mistakenly redefined from UINT32_MAX to UINT64_MAX
on AArch32 when the arch-specific headers were merged.
This value is not currently used by upstream TF-A source code,
so no functionality should be affected.
Change-Id: I2acf7f8736423697c7377e8ed4b08843ced26e66
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
show more ...
|
| fcccd358 | 11-Dec-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "libc: add memrchr" into integration |
| ebff1072 | 19-Jun-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
libc: add memrchr
This function scans a string backwards from the end for the first
instance of a character.
Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763
Signed-off-by: Ambroise Vincent <am
libc: add memrchr
This function scans a string backwards from the end for the first
instance of a character.
Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
show more ...
|
| d0196911 | 18-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
arm: gicv3: Fix compiler dependent behavior
C99 standard: "What constitutes an access to an object that has
volatile-qualified type is implementation-defined".
GCC is not considering the cast to vo
arm: gicv3: Fix compiler dependent behavior
C99 standard: "What constitutes an access to an object that has
volatile-qualified type is implementation-defined".
GCC is not considering the cast to void of volatile structures as an
access and so is not actually issuing reads.
Clang does read those structures by copying them on the stack, which in
this case creates an overflow because of their large size.
This patch removes the cast to void and instead uses the USED attribute
to tell the compiler to retain the static variables.
Change-Id: I952b5056e3f6e91841e7ef9558434352710ab80d
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Zelalem Aweke <zelalem.aweke@arm.com>
show more ...
|
| ade3f5df | 06-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "bs/libc" into integration
* changes:
libc: Consolidate the size_t and NULL definitions
libc: Consolidate unified definitions
libc: Unify intmax_t and uintmax_t on AAr
Merge changes from topic "bs/libc" into integration
* changes:
libc: Consolidate the size_t and NULL definitions
libc: Consolidate unified definitions
libc: Unify intmax_t and uintmax_t on AArch32/64
show more ...
|
| d45c323a | 25-Oct-2019 |
Bence Szépkúti <bence.szepkuti@arm.com> |
libc: Consolidate the size_t and NULL definitions
Consolidate the definition of size_t to one header per AArch, and
the definition of NULL to one header
Signed-off-by: Bence Szépkúti <bence.szepkut
libc: Consolidate the size_t and NULL definitions
Consolidate the definition of size_t to one header per AArch, and
the definition of NULL to one header
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Iecfbad2cf360cfb705ce7aaa981700fd16219b82
show more ...
|