1# 2# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture major and minor versions: 8.0 by default. 23ARM_ARCH_MAJOR := 8 24ARM_ARCH_MINOR := 0 25 26# Base commit to perform code check on 27BASE_COMMIT := origin/master 28 29# Execute BL2 at EL3 30BL2_AT_EL3 := 0 31 32# BL2 image is stored in XIP memory, for now, this option is only supported 33# when BL2_AT_EL3 is 1. 34BL2_IN_XIP_MEM := 0 35 36# Do dcache invalidate upon BL2 entry at EL3 37BL2_INV_DCACHE := 1 38 39# Select the branch protection features to use. 40BRANCH_PROTECTION := 0 41 42# By default, consider that the platform may release several CPUs out of reset. 43# The platform Makefile is free to override this value. 44COLD_BOOT_SINGLE_CPU := 0 45 46# Flag to compile in coreboot support code. Exclude by default. The coreboot 47# Makefile system will set this when compiling TF as part of a coreboot image. 48COREBOOT := 0 49 50# For Chain of Trust 51CREATE_KEYS := 1 52 53# Build flag to include AArch32 registers in cpu context save and restore during 54# world switch. This flag must be set to 0 for AArch64-only platforms. 55CTX_INCLUDE_AARCH32_REGS := 1 56 57# Include FP registers in cpu context 58CTX_INCLUDE_FPREGS := 0 59 60# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 61# must be set to 1 if the platform wants to use this feature in the Secure 62# world. It is not needed to use it in the Non-secure world. 63CTX_INCLUDE_PAUTH_REGS := 0 64 65# Debug build 66DEBUG := 0 67 68# Build platform 69DEFAULT_PLAT := fvp 70 71# Disable the generation of the binary image (ELF only). 72DISABLE_BIN_GENERATION := 0 73 74# Enable capability to disable authentication dynamically. Only meant for 75# development platforms. 76DYN_DISABLE_AUTH := 0 77 78# Build option to enable MPAM for lower ELs 79ENABLE_MPAM_FOR_LOWER_ELS := 0 80 81# Flag to Enable Position Independant support (PIE) 82ENABLE_PIE := 0 83 84# Flag to enable Performance Measurement Framework 85ENABLE_PMF := 0 86 87# Flag to enable PSCI STATs functionality 88ENABLE_PSCI_STAT := 0 89 90# Flag to enable runtime instrumentation using PMF 91ENABLE_RUNTIME_INSTRUMENTATION := 0 92 93# Flag to enable stack corruption protection 94ENABLE_STACK_PROTECTOR := 0 95 96# Flag to enable exception handling in EL3 97EL3_EXCEPTION_HANDLING := 0 98 99# Flag to enable Branch Target Identification. 100# Internal flag not meant for direct setting. 101# Use BRANCH_PROTECTION to enable BTI. 102ENABLE_BTI := 0 103 104# Flag to enable Pointer Authentication. 105# Internal flag not meant for direct setting. 106# Use BRANCH_PROTECTION to enable PAUTH. 107ENABLE_PAUTH := 0 108 109# Build flag to treat usage of deprecated platform and framework APIs as error. 110ERROR_DEPRECATED := 0 111 112# Fault injection support 113FAULT_INJECTION_SUPPORT := 0 114 115# Byte alignment that each component in FIP is aligned to 116FIP_ALIGN := 0 117 118# Default FIP file name 119FIP_NAME := fip.bin 120 121# Default FWU_FIP file name 122FWU_FIP_NAME := fwu_fip.bin 123 124# For Chain of Trust 125GENERATE_COT := 0 126 127# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 128# default, they are for Secure EL1. 129GICV2_G0_FOR_EL3 := 0 130 131# Route External Aborts to EL3. Disabled by default; External Aborts are handled 132# by lower ELs. 133HANDLE_EA_EL3_FIRST := 0 134 135# Whether system coherency is managed in hardware, without explicit software 136# operations. 137HW_ASSISTED_COHERENCY := 0 138 139# Set the default algorithm for the generation of Trusted Board Boot keys 140KEY_ALG := rsa 141 142# NS timer register save and restore 143NS_TIMER_SWITCH := 0 144 145# Include lib/libc in the final image 146OVERRIDE_LIBC := 0 147 148# Build PL011 UART driver in minimal generic UART mode 149PL011_GENERIC_UART := 0 150 151# By default, consider that the platform's reset address is not programmable. 152# The platform Makefile is free to override this value. 153PROGRAMMABLE_RESET_ADDRESS := 0 154 155# Flag used to choose the power state format: Extended State-ID or Original 156PSCI_EXTENDED_STATE_ID := 0 157 158# Enable RAS support 159RAS_EXTENSION := 0 160 161# By default, BL1 acts as the reset handler, not BL31 162RESET_TO_BL31 := 0 163 164# For Chain of Trust 165SAVE_KEYS := 0 166 167# Software Delegated Exception support 168SDEI_SUPPORT := 0 169 170# Whether code and read-only data should be put on separate memory pages. The 171# platform Makefile is free to override this value. 172SEPARATE_CODE_AND_RODATA := 0 173 174# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 175# separate memory region, which may be discontiguous from the rest of BL31. 176SEPARATE_NOBITS_REGION := 0 177 178# If the BL31 image initialisation code is recalimed after use for the secondary 179# cores stack 180RECLAIM_INIT_CODE := 0 181 182# SPD choice 183SPD := none 184 185# Enable the Management Mode (MM)-based Secure Partition Manager implementation 186SPM_MM := 0 187 188# Flag to introduce an infinite loop in BL1 just before it exits into the next 189# image. This is meant to help debugging the post-BL2 phase. 190SPIN_ON_BL1_EXIT := 0 191 192# Flags to build TF with Trusted Boot support 193TRUSTED_BOARD_BOOT := 0 194 195# Build option to choose whether Trusted Firmware uses Coherent memory or not. 196USE_COHERENT_MEM := 1 197 198# Build option to add debugfs support 199USE_DEBUGFS := 0 200 201# Build option to choose whether Trusted Firmware uses library at ROM 202USE_ROMLIB := 0 203 204# Use tbbr_oid.h instead of platform_oid.h 205USE_TBBR_DEFS := 1 206 207# Build verbosity 208V := 0 209 210# Whether to enable D-Cache early during warm boot. This is usually 211# applicable for platforms wherein interconnect programming is not 212# required to enable cache coherency after warm reset (eg: single cluster 213# platforms). 214WARMBOOT_ENABLE_DCACHE_EARLY := 0 215 216# Build option to enable/disable the Statistical Profiling Extensions 217ENABLE_SPE_FOR_LOWER_ELS := 1 218 219# SPE is only supported on AArch64 so disable it on AArch32. 220ifeq (${ARCH},aarch32) 221 override ENABLE_SPE_FOR_LOWER_ELS := 0 222endif 223 224# Include Memory Tagging Extension registers in cpu context. This must be set 225# to 1 if the platform wants to use this feature in the Secure world and MTE is 226# enabled at ELX. 227CTX_INCLUDE_MTE_REGS := 0 228 229ENABLE_AMU := 0 230 231# By default, enable Scalable Vector Extension if implemented for Non-secure 232# lower ELs 233# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 234ifneq (${ARCH},aarch32) 235 ENABLE_SVE_FOR_NS := 1 236else 237 override ENABLE_SVE_FOR_NS := 0 238endif 239 240SANITIZE_UB := off 241 242# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 243# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 244# Default: disabled 245USE_SPINLOCK_CAS := 0 246 247# Enable Link Time Optimization 248ENABLE_LTO := 0 249