1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef T194_NVG_H 8 #define T194_NVG_H 9 10 /** 11 * t194_nvg.h - Header for the NVIDIA Generic interface (NVG). 12 * Official documentation for this interface is included as part 13 * of the T194 TRM. 14 */ 15 16 /** 17 * Current version - Major version increments may break backwards 18 * compatiblity and binary compatibility. Minor version increments 19 * occur when there is only new functionality. 20 */ 21 enum { 22 TEGRA_NVG_VERSION_MAJOR = 6, 23 TEGRA_NVG_VERSION_MINOR = 4 24 }; 25 26 typedef enum { 27 TEGRA_NVG_CHANNEL_VERSION = 0, 28 TEGRA_NVG_CHANNEL_POWER_PERF = 1, 29 TEGRA_NVG_CHANNEL_POWER_MODES = 2, 30 TEGRA_NVG_CHANNEL_WAKE_TIME = 3, 31 TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, 32 TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, 33 TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, 34 TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, 35 TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, 36 TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, 37 TEGRA_NVG_CHANNEL_SHUTDOWN = 42, 38 TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, 39 TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, 40 TEGRA_NVG_CHANNEL_CC3_CTRL = 45, 41 TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, 42 TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, 43 TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, 44 TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, 45 TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, 46 TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, 47 TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, 48 TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, 49 TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, 50 TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60, 51 TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61, 52 TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62, 53 TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63, 54 TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64, 55 TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65, 56 TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66, 57 TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67, 58 TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68, 59 TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69, 60 TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70, 61 TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71, 62 TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72, 63 TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73, 64 TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74, 65 TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75, 66 TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76, 67 TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77, 68 TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78, 69 TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79, 70 71 TEGRA_NVG_CHANNEL_LAST_INDEX 72 } tegra_nvg_channel_id_t; 73 74 typedef enum { 75 NVG_STAT_QUERY_SC7_ENTRIES = 1, 76 NVG_STAT_QUERY_CC6_ENTRIES = 6, 77 NVG_STAT_QUERY_CG7_ENTRIES = 7, 78 NVG_STAT_QUERY_C6_ENTRIES = 10, 79 NVG_STAT_QUERY_C7_ENTRIES = 14, 80 NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, 81 NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, 82 NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, 83 NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, 84 NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56, 85 NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM = 60, 86 NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM = 61, 87 NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM = 62, 88 NVG_STAT_QUERY_C6_ENTRY_TIME_SUM = 63, 89 NVG_STAT_QUERY_C7_ENTRY_TIME_SUM = 64, 90 NVG_STAT_QUERY_SC7_EXIT_TIME_SUM = 70, 91 NVG_STAT_QUERY_CC6_EXIT_TIME_SUM = 71, 92 NVG_STAT_QUERY_CG7_EXIT_TIME_SUM = 72, 93 NVG_STAT_QUERY_C6_EXIT_TIME_SUM = 73, 94 NVG_STAT_QUERY_C7_EXIT_TIME_SUM = 74, 95 NVG_STAT_QUERY_SC7_ENTRY_LAST = 80, 96 NVG_STAT_QUERY_CC6_ENTRY_LAST = 81, 97 NVG_STAT_QUERY_CG7_ENTRY_LAST = 82, 98 NVG_STAT_QUERY_C6_ENTRY_LAST = 83, 99 NVG_STAT_QUERY_C7_ENTRY_LAST = 84, 100 NVG_STAT_QUERY_SC7_EXIT_LAST = 90, 101 NVG_STAT_QUERY_CC6_EXIT_LAST = 91, 102 NVG_STAT_QUERY_CG7_EXIT_LAST = 92, 103 NVG_STAT_QUERY_C6_EXIT_LAST = 93, 104 NVG_STAT_QUERY_C7_EXIT_LAST = 94 105 } tegra_nvg_stat_query_t; 106 107 typedef enum { 108 TEGRA_NVG_CORE_C0 = 0, 109 TEGRA_NVG_CORE_C1 = 1, 110 TEGRA_NVG_CORE_C6 = 6, 111 TEGRA_NVG_CORE_C7 = 7, 112 TEGRA_NVG_CORE_WARMRSTREQ = 8 113 } tegra_nvg_core_sleep_state_t; 114 115 typedef enum { 116 TEGRA_NVG_CLUSTER_CC0 = 0, 117 TEGRA_NVG_CLUSTER_CC6 = 6 118 } tegra_nvg_cluster_sleep_state_t; 119 120 typedef enum { 121 TEGRA_NVG_CG_CG0 = 0, 122 TEGRA_NVG_CG_CG7 = 7 123 } tegra_nvg_cluster_group_sleep_state_t; 124 125 typedef enum { 126 TEGRA_NVG_SYSTEM_SC0 = 0, 127 TEGRA_NVG_SYSTEM_SC7 = 7, 128 TEGRA_NVG_SYSTEM_SC8 = 8 129 } tegra_nvg_system_sleep_state_t; 130 131 typedef enum { 132 TEGRA_NVG_SHUTDOWN = 0U, 133 TEGRA_NVG_REBOOT = 1U, 134 } tegra_nvg_shutdown_reboot_state_t; 135 136 // --------------------------------------------------------------------------- 137 // NVG Data subformats 138 // --------------------------------------------------------------------------- 139 140 typedef union { 141 uint64_t flat; 142 struct nvg_version_channel_t { 143 uint32_t minor_version : 32; 144 uint32_t major_version : 32; 145 } bits; 146 } nvg_version_data_t; 147 148 typedef union { 149 uint64_t flat; 150 struct nvg_power_perf_channel_t { 151 uint32_t perf_per_watt : 1; 152 uint32_t reserved_31_1 : 31; 153 uint32_t reserved_63_32 : 32; 154 } bits; 155 } nvg_power_perf_channel_t; 156 157 typedef union { 158 uint64_t flat; 159 struct nvg_power_modes_channel_t { 160 uint32_t low_battery : 1; 161 uint32_t reserved_1_1 : 1; 162 uint32_t battery_save : 1; 163 uint32_t reserved_31_3 : 29; 164 uint32_t reserved_63_32 : 32; 165 } bits; 166 } nvg_power_modes_channel_t; 167 168 typedef union nvg_channel_1_data_u { 169 uint64_t flat; 170 struct nvg_channel_1_data_s { 171 uint32_t perf_per_watt_mode : 1; 172 uint32_t reserved_31_1 : 31; 173 uint32_t reserved_63_32 : 32; 174 } bits; 175 } nvg_channel_1_data_t; 176 177 typedef union { 178 uint64_t flat; 179 struct nvg_ccplex_cache_control_channel_t { 180 uint32_t gpu_ways : 5; 181 uint32_t reserved_7_5 : 3; 182 uint32_t gpu_only_ways : 5; 183 uint32_t reserved_31_13 : 19; 184 uint32_t reserved_63_32 : 32; 185 } bits; 186 } nvg_ccplex_cache_control_channel_t; 187 188 typedef union nvg_channel_2_data_u { 189 uint64_t flat; 190 struct nvg_channel_2_data_s { 191 uint32_t reserved_1_0 : 2; 192 uint32_t battery_saver_mode : 1; 193 uint32_t reserved_31_3 : 29; 194 uint32_t reserved_63_32 : 32; 195 } bits; 196 } nvg_channel_2_data_t; 197 198 typedef union { 199 uint64_t flat; 200 struct nvg_wake_time_channel_t { 201 uint32_t wake_time : 32; 202 uint32_t reserved_63_32 : 32; 203 } bits; 204 } nvg_wake_time_channel_t; 205 206 typedef union { 207 uint64_t flat; 208 struct nvg_cstate_info_channel_t { 209 uint32_t cluster_state : 3; 210 uint32_t reserved_6_3 : 4; 211 uint32_t update_cluster : 1; 212 uint32_t cg_cstate : 3; 213 uint32_t reserved_14_11 : 4; 214 uint32_t update_cg : 1; 215 uint32_t system_cstate : 4; 216 uint32_t reserved_22_20 : 3; 217 uint32_t update_system : 1; 218 uint32_t reserved_30_24 : 7; 219 uint32_t update_wake_mask : 1; 220 uint32_t wake_mask : 32; 221 } bits; 222 } nvg_cstate_info_channel_t; 223 224 typedef union { 225 uint64_t flat; 226 struct nvg_lower_bound_channel_t { 227 uint32_t crossover_value : 32; 228 uint32_t reserved_63_32 : 32; 229 } bits; 230 } nvg_lower_bound_channel_t; 231 232 typedef union { 233 uint64_t flat; 234 struct nvg_cstate_stat_query_channel_t { 235 uint32_t unit_id : 4; 236 uint32_t reserved_15_4 : 12; 237 uint32_t stat_id : 16; 238 uint32_t reserved_63_32 : 32; 239 } bits; 240 } nvg_cstate_stat_query_channel_t; 241 242 typedef union { 243 uint64_t flat; 244 struct nvg_is_sc7_allowed_channel_t { 245 uint32_t is_sc7_allowed : 1; 246 uint32_t reserved_31_1 : 31; 247 uint32_t reserved_63_32 : 32; 248 } bits; 249 } nvg_is_sc7_allowed_channel_t; 250 251 typedef union { 252 uint64_t flat; 253 struct nvg_core_online_channel_t { 254 uint32_t core_id : 4; 255 uint32_t reserved_31_4 : 28; 256 uint32_t reserved_63_32 : 32; 257 } bits; 258 } nvg_core_online_channel_t; 259 260 typedef union { 261 uint64_t flat; 262 struct nvg_cc3_control_channel_t { 263 uint32_t freq_req : 8; 264 uint32_t reserved_30_8 : 23; 265 uint32_t enable : 1; 266 uint32_t reserved_63_32 : 32; 267 } bits; 268 } nvg_cc3_control_channel_t; 269 270 typedef enum { 271 TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0, 272 TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1, 273 TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2, 274 TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3, 275 TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4, 276 TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5, 277 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6, 278 TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7, 279 TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8, 280 TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9, 281 TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, 282 TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, 283 TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, 284 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, 285 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, 286 TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, 287 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, 288 TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, 289 TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, 290 TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, 291 TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, 292 TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, 293 TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, 294 TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, 295 TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, 296 TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, 297 TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, 298 TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, 299 TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, 300 TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, 301 TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, 302 TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, 303 TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, 304 TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, 305 TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, 306 TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, 307 TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX 308 } tegra_nvg_channel_update_gsc_gsc_enum_t; 309 310 typedef union { 311 uint64_t flat; 312 struct nvg_update_ccplex_gsc_channel_t { 313 uint32_t gsc_enum : 16; 314 uint32_t reserved_31_16 : 16; 315 uint32_t reserved_63_32 : 32; 316 } bits; 317 } nvg_update_ccplex_gsc_channel_t; 318 319 typedef union { 320 uint64_t flat; 321 struct nvg_security_config_channel_t { 322 uint32_t strict_checking_enabled : 1; 323 uint32_t strict_checking_locked : 1; 324 uint32_t reserved_31_2 : 30; 325 uint32_t reserved_63_32 : 32; 326 } bits; 327 } nvg_security_config_t; 328 329 typedef union { 330 uint64_t flat; 331 struct nvg_shutdown_channel_t { 332 uint32_t reboot : 1; 333 uint32_t reserved_31_1 : 31; 334 uint32_t reserved_63_32 : 32; 335 } bits; 336 } nvg_shutdown_t; 337 338 #endif 339