1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/arm/css/css_scp.h> 13 #include <drivers/arm/css/scmi.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/arm/css/common/css_pm.h> 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 /* 20 * This file implements the SCP helper functions using SCMI protocol. 21 */ 22 23 /* 24 * SCMI power state parameter bit field encoding for ARM CSS platforms. 25 * 26 * 31 20 19 16 15 12 11 8 7 4 3 0 27 * +-------------------------------------------------------------+ 28 * | SBZ | Max level | Level 3 | Level 2 | Level 1 | Level 0 | 29 * | | | state | state | state | state | 30 * +-------------------------------------------------------------+ 31 * 32 * `Max level` encodes the highest level that has a valid power state 33 * encoded in the power state. 34 */ 35 #define SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT 16 36 #define SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH 4 37 #define SCMI_PWR_STATE_MAX_PWR_LVL_MASK \ 38 ((1 << SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH) - 1) 39 #define SCMI_SET_PWR_STATE_MAX_PWR_LVL(_power_state, _max_level) \ 40 (_power_state) |= ((_max_level) & SCMI_PWR_STATE_MAX_PWR_LVL_MASK)\ 41 << SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT 42 #define SCMI_GET_PWR_STATE_MAX_PWR_LVL(_power_state) \ 43 (((_power_state) >> SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT) \ 44 & SCMI_PWR_STATE_MAX_PWR_LVL_MASK) 45 46 #define SCMI_PWR_STATE_LVL_WIDTH 4 47 #define SCMI_PWR_STATE_LVL_MASK \ 48 ((1 << SCMI_PWR_STATE_LVL_WIDTH) - 1) 49 #define SCMI_SET_PWR_STATE_LVL(_power_state, _level, _level_state) \ 50 (_power_state) |= ((_level_state) & SCMI_PWR_STATE_LVL_MASK) \ 51 << (SCMI_PWR_STATE_LVL_WIDTH * (_level)) 52 #define SCMI_GET_PWR_STATE_LVL(_power_state, _level) \ 53 (((_power_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (_level))) & \ 54 SCMI_PWR_STATE_LVL_MASK) 55 56 /* 57 * The SCMI power state enumeration for a power domain level 58 */ 59 typedef enum { 60 scmi_power_state_off = 0, 61 scmi_power_state_on = 1, 62 scmi_power_state_sleep = 2, 63 } scmi_power_state_t; 64 65 /* 66 * The global handle for invoking the SCMI driver APIs after the driver 67 * has been initialized. 68 */ 69 static void *scmi_handle; 70 71 /* The SCMI channel global object */ 72 static scmi_channel_t channel; 73 74 ARM_SCMI_INSTANTIATE_LOCK; 75 76 /* 77 * Helper function to suspend a CPU power domain and its parent power domains 78 * if applicable. 79 */ 80 void css_scp_suspend(const struct psci_power_state *target_state) 81 { 82 int ret; 83 84 /* At least power domain level 0 should be specified to be suspended */ 85 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 86 ARM_LOCAL_STATE_OFF); 87 88 /* Check if power down at system power domain level is requested */ 89 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { 90 /* Issue SCMI command for SYSTEM_SUSPEND */ 91 ret = scmi_sys_pwr_state_set(scmi_handle, 92 SCMI_SYS_PWR_FORCEFUL_REQ, 93 SCMI_SYS_PWR_SUSPEND); 94 if (ret != SCMI_E_SUCCESS) { 95 ERROR("SCMI system power domain suspend return 0x%x unexpected\n", 96 ret); 97 panic(); 98 } 99 return; 100 } 101 #if !HW_ASSISTED_COHERENCY 102 unsigned int lvl; 103 uint32_t scmi_pwr_state = 0; 104 /* 105 * If we reach here, then assert that power down at system power domain 106 * level is running. 107 */ 108 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); 109 110 /* For level 0, specify `scmi_power_state_sleep` as the power state */ 111 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, ARM_PWR_LVL0, 112 scmi_power_state_sleep); 113 114 for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { 115 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) 116 break; 117 118 assert(target_state->pwr_domain_state[lvl] == 119 ARM_LOCAL_STATE_OFF); 120 /* 121 * Specify `scmi_power_state_off` as power state for higher 122 * levels. 123 */ 124 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, 125 scmi_power_state_off); 126 } 127 128 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); 129 130 ret = scmi_pwr_state_set(scmi_handle, 131 plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()], 132 scmi_pwr_state); 133 134 if (ret != SCMI_E_SUCCESS) { 135 ERROR("SCMI set power state command return 0x%x unexpected\n", 136 ret); 137 panic(); 138 } 139 #endif 140 } 141 142 /* 143 * Helper function to turn off a CPU power domain and its parent power domains 144 * if applicable. 145 */ 146 void css_scp_off(const struct psci_power_state *target_state) 147 { 148 unsigned int lvl = 0; 149 int ret; 150 uint32_t scmi_pwr_state = 0; 151 152 /* At-least the CPU level should be specified to be OFF */ 153 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 154 ARM_LOCAL_STATE_OFF); 155 156 /* PSCI CPU OFF cannot be used to turn OFF system power domain */ 157 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); 158 159 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { 160 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) 161 break; 162 163 assert(target_state->pwr_domain_state[lvl] == 164 ARM_LOCAL_STATE_OFF); 165 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, 166 scmi_power_state_off); 167 } 168 169 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); 170 171 ret = scmi_pwr_state_set(scmi_handle, 172 plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()], 173 scmi_pwr_state); 174 175 if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { 176 ERROR("SCMI set power state command return 0x%x unexpected\n", 177 ret); 178 panic(); 179 } 180 } 181 182 /* 183 * Helper function to turn ON a CPU power domain and its parent power domains 184 * if applicable. 185 */ 186 void css_scp_on(u_register_t mpidr) 187 { 188 unsigned int lvl = 0; 189 int core_pos, ret; 190 uint32_t scmi_pwr_state = 0; 191 192 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) 193 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, 194 scmi_power_state_on); 195 196 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); 197 198 core_pos = plat_core_pos_by_mpidr(mpidr); 199 assert((core_pos >= 0) && 200 (((unsigned int)core_pos) < PLATFORM_CORE_COUNT)); 201 202 ret = scmi_pwr_state_set(scmi_handle, 203 plat_css_core_pos_to_scmi_dmn_id_map[core_pos], 204 scmi_pwr_state); 205 206 if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { 207 ERROR("SCMI set power state command return 0x%x unexpected\n", 208 ret); 209 panic(); 210 } 211 } 212 213 /* 214 * Helper function to get the power state of a power domain node as reported 215 * by the SCP. 216 */ 217 int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level) 218 { 219 int ret, cpu_idx; 220 uint32_t scmi_pwr_state = 0, lvl_state; 221 222 /* We don't support get power state at the system power domain level */ 223 if ((power_level > PLAT_MAX_PWR_LVL) || 224 (power_level == CSS_SYSTEM_PWR_DMN_LVL)) { 225 WARN("Invalid power level %u specified for SCMI get power state\n", 226 power_level); 227 return PSCI_E_INVALID_PARAMS; 228 } 229 230 cpu_idx = plat_core_pos_by_mpidr(mpidr); 231 assert(cpu_idx > -1); 232 233 ret = scmi_pwr_state_get(scmi_handle, 234 plat_css_core_pos_to_scmi_dmn_id_map[cpu_idx], 235 &scmi_pwr_state); 236 237 if (ret != SCMI_E_SUCCESS) { 238 WARN("SCMI get power state command return 0x%x unexpected\n", 239 ret); 240 return PSCI_E_INVALID_PARAMS; 241 } 242 243 /* 244 * Find the maximum power level described in the get power state 245 * command. If it is less than the requested power level, then assume 246 * the requested power level is ON. 247 */ 248 if (SCMI_GET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state) < power_level) 249 return HW_ON; 250 251 lvl_state = SCMI_GET_PWR_STATE_LVL(scmi_pwr_state, power_level); 252 if (lvl_state == scmi_power_state_on) 253 return HW_ON; 254 255 assert((lvl_state == scmi_power_state_off) || 256 (lvl_state == scmi_power_state_sleep)); 257 return HW_OFF; 258 } 259 260 void __dead2 css_scp_system_off(int state) 261 { 262 int ret; 263 264 /* 265 * Disable GIC CPU interface to prevent pending interrupt from waking 266 * up the AP from WFI. 267 */ 268 plat_arm_gic_cpuif_disable(); 269 270 /* 271 * Issue SCMI command. First issue a graceful 272 * request and if that fails force the request. 273 */ 274 ret = scmi_sys_pwr_state_set(scmi_handle, 275 SCMI_SYS_PWR_FORCEFUL_REQ, 276 state); 277 278 if (ret != SCMI_E_SUCCESS) { 279 ERROR("SCMI system power state set 0x%x returns unexpected 0x%x\n", 280 state, ret); 281 panic(); 282 } 283 wfi(); 284 ERROR("CSS set power state: operation not handled.\n"); 285 panic(); 286 } 287 288 /* 289 * Helper function to shutdown the system via SCMI. 290 */ 291 void __dead2 css_scp_sys_shutdown(void) 292 { 293 css_scp_system_off(SCMI_SYS_PWR_SHUTDOWN); 294 } 295 296 /* 297 * Helper function to reset the system via SCMI. 298 */ 299 void __dead2 css_scp_sys_reboot(void) 300 { 301 css_scp_system_off(SCMI_SYS_PWR_COLD_RESET); 302 } 303 304 static int scmi_ap_core_init(scmi_channel_t *ch) 305 { 306 #if PROGRAMMABLE_RESET_ADDRESS 307 uint32_t version; 308 int ret; 309 310 ret = scmi_proto_version(ch, SCMI_AP_CORE_PROTO_ID, &version); 311 if (ret != SCMI_E_SUCCESS) { 312 WARN("SCMI AP core protocol version message failed\n"); 313 return -1; 314 } 315 316 if (!is_scmi_version_compatible(SCMI_AP_CORE_PROTO_VER, version)) { 317 WARN("SCMI AP core protocol version 0x%x incompatible with driver version 0x%x\n", 318 version, SCMI_AP_CORE_PROTO_VER); 319 return -1; 320 } 321 INFO("SCMI AP core protocol version 0x%x detected\n", version); 322 #endif 323 return 0; 324 } 325 326 void __init plat_arm_pwrc_setup(void) 327 { 328 channel.info = plat_css_get_scmi_info(); 329 channel.lock = ARM_SCMI_LOCK_GET_INSTANCE; 330 scmi_handle = scmi_init(&channel); 331 if (scmi_handle == NULL) { 332 ERROR("SCMI Initialization failed\n"); 333 panic(); 334 } 335 if (scmi_ap_core_init(&channel) < 0) { 336 ERROR("SCMI AP core protocol initialization failed\n"); 337 panic(); 338 } 339 } 340 341 /****************************************************************************** 342 * This function overrides the default definition for ARM platforms. Initialize 343 * the SCMI driver, query capability via SCMI and modify the PSCI capability 344 * based on that. 345 *****************************************************************************/ 346 const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops) 347 { 348 uint32_t msg_attr; 349 int ret; 350 351 assert(scmi_handle); 352 353 /* Check that power domain POWER_STATE_SET message is supported */ 354 ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID, 355 SCMI_PWR_STATE_SET_MSG, &msg_attr); 356 if (ret != SCMI_E_SUCCESS) { 357 ERROR("Set power state command is not supported by SCMI\n"); 358 panic(); 359 } 360 361 /* 362 * Don't support PSCI NODE_HW_STATE call if SCMI doesn't support 363 * POWER_STATE_GET message. 364 */ 365 ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID, 366 SCMI_PWR_STATE_GET_MSG, &msg_attr); 367 if (ret != SCMI_E_SUCCESS) 368 ops->get_node_hw_state = NULL; 369 370 /* Check if the SCMI SYSTEM_POWER_STATE_SET message is supported */ 371 ret = scmi_proto_msg_attr(scmi_handle, SCMI_SYS_PWR_PROTO_ID, 372 SCMI_SYS_PWR_STATE_SET_MSG, &msg_attr); 373 if (ret != SCMI_E_SUCCESS) { 374 /* System power management operations are not supported */ 375 ops->system_off = NULL; 376 ops->system_reset = NULL; 377 ops->get_sys_suspend_power_state = NULL; 378 } else { 379 if (!(msg_attr & SCMI_SYS_PWR_SUSPEND_SUPPORTED)) { 380 /* 381 * System power management protocol is available, but 382 * it does not support SYSTEM SUSPEND. 383 */ 384 ops->get_sys_suspend_power_state = NULL; 385 } 386 if (!(msg_attr & SCMI_SYS_PWR_WARM_RESET_SUPPORTED)) { 387 /* 388 * WARM reset is not available. 389 */ 390 ops->system_reset2 = NULL; 391 } 392 } 393 394 return ops; 395 } 396 397 int css_system_reset2(int is_vendor, int reset_type, u_register_t cookie) 398 { 399 if (is_vendor || (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET)) 400 return PSCI_E_INVALID_PARAMS; 401 402 css_scp_system_off(SCMI_SYS_PWR_WARM_RESET); 403 /* 404 * css_scp_system_off cannot return (it is a __dead function), 405 * but css_system_reset2 has to return some value, even in 406 * this case. 407 */ 408 return 0; 409 } 410 411 #if PROGRAMMABLE_RESET_ADDRESS 412 void plat_arm_program_trusted_mailbox(uintptr_t address) 413 { 414 int ret; 415 416 assert(scmi_handle); 417 ret = scmi_ap_core_set_reset_addr(scmi_handle, address, 418 SCMI_AP_CORE_LOCK_ATTR); 419 if (ret != SCMI_E_SUCCESS) { 420 ERROR("CSS: Failed to program reset address: %d\n", ret); 421 panic(); 422 } 423 } 424 #endif 425