| e747a59b | 24-May-2021 |
Chris Kay <chris.kay@arm.com> |
refactor(amu): refactor enablement and context switching
This change represents a general refactoring to clean up old code that
has been adapted to account for changes required to enable dynamic
aux
refactor(amu): refactor enablement and context switching
This change represents a general refactoring to clean up old code that
has been adapted to account for changes required to enable dynamic
auxiliary counters.
Change-Id: Ia85e0518f3f65c765f07b34b67744fc869b9070d
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| 31d3cc25 | 25-May-2021 |
Chris Kay <chris.kay@arm.com> |
refactor(amu): detect auxiliary counters at runtime
This change decouples the group 1 counter macros to facilitate dynamic
detection at runtime. These counters remain disabled - we will add
dynamic
refactor(amu): detect auxiliary counters at runtime
This change decouples the group 1 counter macros to facilitate dynamic
detection at runtime. These counters remain disabled - we will add
dynamic enablement of them in a later patch.
Change-Id: I820d05f228d440643bdfa308d030bd51ebc0b35a
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| 81e2ff1f | 25-May-2021 |
Chris Kay <chris.kay@arm.com> |
refactor(amu): detect architected counters at runtime
This change removes the `AMU_GROUP0_COUNTERS_MASK` and
`AMU_GROUP0_MAX_COUNTERS` preprocessor definitions, instead retrieving
the number of grou
refactor(amu): detect architected counters at runtime
This change removes the `AMU_GROUP0_COUNTERS_MASK` and
`AMU_GROUP0_MAX_COUNTERS` preprocessor definitions, instead retrieving
the number of group 0 counters dynamically through `AMCGCR_EL0.CG0NC`.
Change-Id: I70e39c30fbd5df89b214276fac79cc8758a89f72
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| 1fd685a7 | 25-May-2021 |
Chris Kay <chris.kay@arm.com> |
refactor(amu): conditionally compile auxiliary counter support
This change reduces preprocessor dependencies on the
`AMU_GROUP1_NR_COUNTERS` and `AMU_GROUP1_COUNTERS_MASK` definitions, as
these valu
refactor(amu): conditionally compile auxiliary counter support
This change reduces preprocessor dependencies on the
`AMU_GROUP1_NR_COUNTERS` and `AMU_GROUP1_COUNTERS_MASK` definitions, as
these values will eventually be discovered dynamically.
In their stead, we introduce the `ENABLE_AMU_AUXILIARY_COUNTERS` build
option, which will enable support for dynamically detecting and
enabling auxiliary AMU counters.
This substantially reduces the amount of memory used by platforms that
know ahead of time that they do not have any auxiliary AMU counters.
Change-Id: I3d998aff44ed5489af4857e337e97634d06e3ea1
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| b4b726ea | 24-May-2021 |
Chris Kay <chris.kay@arm.com> |
refactor(amu)!: privatize unused AMU APIs
This change reduces the exposed surface area of the AMU API in order to
simplify the refactoring work in following patches. The functions and
definitions pr
refactor(amu)!: privatize unused AMU APIs
This change reduces the exposed surface area of the AMU API in order to
simplify the refactoring work in following patches. The functions and
definitions privatized by this change are not used by other parts of the
code-base today.
BREAKING CHANGE: The public AMU API has been reduced to enablement only
to facilitate refactoring work. These APIs were not previously used.
Change-Id: Ibf6174fb5b3949de3c4ba6847cce47d82a6bd08c
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| 6c8dda19 | 17-May-2021 |
Chris Kay <chris.kay@arm.com> |
refactor(amu)!: remove `PLAT_AMU_GROUP1_COUNTERS_MASK`
With the introduction of MPMM, the auxiliary AMU counter logic requires
refactoring to move away from a single platform-defined group 1 counter
refactor(amu)!: remove `PLAT_AMU_GROUP1_COUNTERS_MASK`
With the introduction of MPMM, the auxiliary AMU counter logic requires
refactoring to move away from a single platform-defined group 1 counter
mask in order to support microarchitectural (per-core) group 1 counters.
BREAKING CHANGE: The `PLAT_AMU_GROUP1_COUNTERS_MASK` platform definition
has been removed. Platforms should specify per-core AMU counter masks
via FCONF or a platform-specific mechanism going forward.
Change-Id: I1e852797c7954f92409222b066a1ae57bc72bb05
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| 4cb576a0 | 15-Oct-2021 |
johpow01 <john.powell@arm.com> |
fix(cpu): correct Demeter CPU name
This patch changes Cortex Demeter to Neoverse Demeter.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7306d09ca60e101d0a96c9ceff9845422d75c160 |
| fb9e5f7b | 19-Aug-2021 |
johpow01 <john.powell@arm.com> |
feat(cpu): add support for Hunter CPU
This patch adds the basic CPU library code to support the Hunter CPU
in TF-A. This CPU is based on the Makalu core so that library code
was adapted as the basis
feat(cpu): add support for Hunter CPU
This patch adds the basic CPU library code to support the Hunter CPU
in TF-A. This CPU is based on the Makalu core so that library code
was adapted as the basis for this patch.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I956b2dc0f43da7cec3e015252392e2694363e1b3
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|
| eab78e9b | 10-Aug-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(measured_boot): remove passing of BL2 hash via device tree
Subsequent patches will provide a solution to do the BL2 hash measurement
and recording in BL1 itself, hence in preparation to ado
refactor(measured_boot): remove passing of BL2 hash via device tree
Subsequent patches will provide a solution to do the BL2 hash measurement
and recording in BL1 itself, hence in preparation to adopt that solution
remove the logic of passing BL2 hash measurement to BL2 component
via TB_FW config.
Change-Id: Iff9b3d4c6a236a33b942898fcdf799cbab89b724
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 1d651211 | 06-Oct-2021 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "za/feat_rme" into integration
* changes:
refactor(gpt): productize and refactor GPT library
feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled
docs(rme
Merge changes from topic "za/feat_rme" into integration
* changes:
refactor(gpt): productize and refactor GPT library
feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled
docs(rme): add build and run instructions for FEAT_RME
fix(plat/fvp): bump BL2 stack size
fix(plat/fvp): allow changing the kernel DTB load address
refactor(plat/arm): rename ARM_DTB_DRAM_NS region macros
refactor(plat/fvp): update FVP platform DTS for FEAT_RME
feat(plat/arm): add GPT initialization code for Arm platforms
feat(plat/fvp): add memory map for FVP platform for FEAT_RME
refactor(plat/arm): modify memory region attributes to account for FEAT_RME
feat(plat/fvp): add RMM image support for FVP platform
feat(rme): add GPT Library
feat(rme): add ENABLE_RME build option and support for RMM image
refactor(makefile): remove BL prefixes in build macros
feat(rme): add context management changes for FEAT_RME
feat(rme): add Test Realm Payload (TRP)
feat(rme): add RMM dispatcher (RMMD)
feat(rme): run BL2 in root world when FEAT_RME is enabled
feat(rme): add xlat table library changes for FEAT_RME
feat(rme): add Realm security state definition
feat(rme): add register definitions and helper functions for FEAT_RME
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|
| f19dc624 | 16-Jun-2021 |
johpow01 <john.powell@arm.com> |
refactor(gpt): productize and refactor GPT library
This patch updates and refactors the GPT library and fixes bugs.
- Support all combinations of PGS, PPS, and L0GPTSZ parameters.
- PPS and PGS are
refactor(gpt): productize and refactor GPT library
This patch updates and refactors the GPT library and fixes bugs.
- Support all combinations of PGS, PPS, and L0GPTSZ parameters.
- PPS and PGS are set at runtime, L0GPTSZ is read from GPCCR_EL3.
- Use compiler definitions to simplify code.
- Renaming functions to better suit intended uses.
- MMU enabled before GPT APIs called.
- Add comments to make function usage more clear in GPT library.
- Added _rme suffix to file names to differentiate better from the
GPT file system code.
- Renamed gpt_defs.h to gpt_rme_private.h to better separate private
and public code.
- Renamed gpt_core.c to gpt_rme.c to better conform to TF-A precedent.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4cbb23b0f81e697baa9fb23ba458aa3f7d1ed919
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|
| de278f33 | 05-Oct-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(errata): workaround for Cortex-A710 erratum 2058056" into integration |
| e2f4b434 | 05-Oct-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes If7dec725,Iedcb84a7,Ife0a4bec into integration
* changes:
errata: workaround for Cortex-A78 erratum 2132060
errata: workaround for Neoverse-V1 erratum 2108267
fix(errata): workar
Merge changes If7dec725,Iedcb84a7,Ife0a4bec into integration
* changes:
errata: workaround for Cortex-A78 erratum 2132060
errata: workaround for Neoverse-V1 erratum 2108267
fix(errata): workaround for Neoverse-N2 erratum 2138953
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|
| 1839012d | 13-Jul-2021 |
Zelalem Aweke <zelalem.aweke@arm.com> |
feat(rme): add GPT Library
This patch introduces the Granule Protection Table (GPT)
library code. This implementation will be updated later to
be more flexible, as the current implementation is very
feat(rme): add GPT Library
This patch introduces the Granule Protection Table (GPT)
library code. This implementation will be updated later to
be more flexible, as the current implementation is very rigid.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I3af824a28c6e9a5d36459c0c51d2d9bebfba1505
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|
| c5ea4f8a | 09-Jul-2021 |
Zelalem Aweke <zelalem.aweke@arm.com> |
feat(rme): add context management changes for FEAT_RME
This patch adds a new context for realm world and realm world
awareness in context management.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm
feat(rme): add context management changes for FEAT_RME
This patch adds a new context for realm world and realm world
awareness in context management.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: Ic17469393603e789d7adc025880346bc3d6233d7
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|
| 36218238 | 08-Jul-2021 |
Zelalem Aweke <zelalem.aweke@arm.com> |
feat(rme): add xlat table library changes for FEAT_RME
FEAT_RME adds a new bit (NSE) in the translation table descriptor
to determine the Physical Address Space (PAS) of an EL3 stage 1
translation a
feat(rme): add xlat table library changes for FEAT_RME
FEAT_RME adds a new bit (NSE) in the translation table descriptor
to determine the Physical Address Space (PAS) of an EL3 stage 1
translation according to the following mapping:
TTD.NSE TTD.NS | PAS
=================================
0 0 | Secure
0 1 | Non-secure
1 0 | Root
1 1 | Realm
This patch adds modifications to version 2 of the translation table
library accordingly. Bits 4 and 5 in mmap attribute are used to
determine the PAS.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I82790f6900b7a1ab9494c732eac7b9808a388103
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|
| 4693ff72 | 08-Jul-2021 |
Zelalem Aweke <zelalem.aweke@arm.com> |
feat(rme): add Realm security state definition
FEAT_RME introduces two additional security states,
Root and Realm security states. This patch adds Realm
security state awareness to SMCCC helpers and
feat(rme): add Realm security state definition
FEAT_RME introduces two additional security states,
Root and Realm security states. This patch adds Realm
security state awareness to SMCCC helpers and entry point info
structure.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I9cdefcc1aa71259b2de46e5fb62b28d658fa59bd
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|
| b36fe212 | 29-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Cortex-A78 erratum 2132060
Cortex-A78 erratum 2132060 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open.
The workaround is to wr
errata: workaround for Cortex-A78 erratum 2132060
Cortex-A78 erratum 2132060 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open.
The workaround is to write the value 2'b11 to the PF_MODE bits
in the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: If7dec72578633d37d110d103099e406c3a970ff7
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|
| 8e140272 | 28-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Neoverse-V1 erratum 2108267
Neoverse-V1 erratum 2108267 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r1p1 of CPU. It is still open. The
workaround is to write
errata: workaround for Neoverse-V1 erratum 2108267
Neoverse-V1 erratum 2108267 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r1p1 of CPU. It is still open. The
workaround is to write the value 2'b11 to the PF_MODE bits in
the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Iedcb84a7ad34af7083116818f49d7296f7d9bf94
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|
| ef8f0c52 | 28-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
fix(errata): workaround for Neoverse-N2 erratum 2138953
Neoverse-N2 erratum 2138953 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to write the value 4'
fix(errata): workaround for Neoverse-N2 erratum 2138953
Neoverse-N2 erratum 2138953 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Ife0a4bece7ccf83cc99c1d5f5b5a43084bb69d64
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|
| 744bdbf7 | 22-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
fix(errata): workaround for Cortex-A710 erratum 2058056
Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write th
fix(errata): workaround for Cortex-A710 erratum 2058056
Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I7ce5181b3b469fbbb16501e633116e119b8bf4f1
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|
| fe82bcc0 | 30-Sep-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "feat(cpu): add support for Hayes CPU" into integration |
| 7bd8dfb8 | 19-Aug-2021 |
johpow01 <john.powell@arm.com> |
feat(cpu): add support for Hayes CPU
This patch adds the basic CPU library code to support the Hayes CPU
in TF-A. This CPU is based on the Klein core so that library code
has been adapted for use he
feat(cpu): add support for Hayes CPU
This patch adds the basic CPU library code to support the Hayes CPU
in TF-A. This CPU is based on the Klein core so that library code
has been adapted for use here.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If0e0070cfa77fee8f6eebfee13d3c4f209ad84fc
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|
| e31fb0fa | 03-Mar-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
fvp_r: load, auth, and transfer from BL1 to BL33
Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.
Signed-off-by: Lauren Wehrme
fvp_r: load, auth, and transfer from BL1 to BL33
Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I293cad09739dacac0d20dd57c1d98178dbe84d40
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|
| 114785c9 | 29-Sep-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Cortex-A710 erratum 2083908" into integration |