1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 11 #define PLAT_PRIMARY_CPU 0x0 12 13 #define MT_GIC_BASE 0x0c000000 14 #define PLAT_MT_CCI_BASE 0x0c500000 15 #define MCUCFG_BASE 0x0c530000 16 17 #define IO_PHYS 0x10000000 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE IO_PHYS 21 #define MTK_DEV_RNG0_SIZE 0x10000000 22 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000) 23 #define MTK_DEV_RNG1_SIZE 0x10000000 24 #define MTK_DEV_RNG2_BASE 0x0c000000 25 #define MTK_DEV_RNG2_SIZE 0x600000 26 27 #define GPIO_BASE (IO_PHYS + 0x00005000) 28 #define IOCFG_RM_BASE (IO_PHYS + 0x01C20000) 29 #define IOCFG_BM_BASE (IO_PHYS + 0x01D10000) 30 #define IOCFG_BL_BASE (IO_PHYS + 0x01D30000) 31 #define IOCFG_BR_BASE (IO_PHYS + 0x01D40000) 32 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 33 #define IOCFG_LB_BASE (IO_PHYS + 0x01E70000) 34 #define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) 35 #define IOCFG_LT_BASE (IO_PHYS + 0x01F20000) 36 #define IOCFG_TL_BASE (IO_PHYS + 0x01F30000) 37 /******************************************************************************* 38 * UART related constants 39 ******************************************************************************/ 40 #define UART0_BASE (IO_PHYS + 0x01002000) 41 #define UART1_BASE (IO_PHYS + 0x01003000) 42 43 #define UART_BAUDRATE 115200 44 45 /******************************************************************************* 46 * System counter frequency related constants 47 ******************************************************************************/ 48 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 49 #define SYS_COUNTER_FREQ_IN_MHZ 13 50 51 /******************************************************************************* 52 * GIC-400 & interrupt handling related constants 53 ******************************************************************************/ 54 55 /* Base MTK_platform compatible GIC memory map */ 56 #define BASE_GICD_BASE MT_GIC_BASE 57 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 58 59 /******************************************************************************* 60 * Platform binary types for linking 61 ******************************************************************************/ 62 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 63 #define PLATFORM_LINKER_ARCH aarch64 64 65 /******************************************************************************* 66 * Generic platform constants 67 ******************************************************************************/ 68 #define PLATFORM_STACK_SIZE 0x800 69 70 #define PLAT_MAX_PWR_LVL U(2) 71 #define PLAT_MAX_RET_STATE U(1) 72 #define PLAT_MAX_OFF_STATE U(2) 73 74 #define PLATFORM_SYSTEM_COUNT U(1) 75 #define PLATFORM_CLUSTER_COUNT U(1) 76 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 77 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 78 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 79 80 #define SOC_CHIP_ID U(0x8192) 81 82 /******************************************************************************* 83 * Platform memory map related constants 84 ******************************************************************************/ 85 #define TZRAM_BASE 0x54600000 86 #define TZRAM_SIZE 0x00030000 87 88 /******************************************************************************* 89 * BL31 specific defines. 90 ******************************************************************************/ 91 /* 92 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 93 * present). BL31_BASE is calculated using the current BL31 debug size plus a 94 * little space for growth. 95 */ 96 #define BL31_BASE (TZRAM_BASE + 0x1000) 97 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 98 99 /******************************************************************************* 100 * Platform specific page table and MMU setup constants 101 ******************************************************************************/ 102 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 103 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 104 #define MAX_XLAT_TABLES 16 105 #define MAX_MMAP_REGIONS 16 106 107 /******************************************************************************* 108 * Declarations and constants to access the mailboxes safely. Each mailbox is 109 * aligned on the biggest cache line size in the platform. This is known only 110 * to the platform as it might have a combination of integrated and external 111 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 112 * line at any cache level. They could belong to different cpus/clusters & 113 * get written while being protected by different locks causing corruption of 114 * a valid mailbox address. 115 ******************************************************************************/ 116 #define CACHE_WRITEBACK_SHIFT 6 117 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 118 #endif /* PLATFORM_DEF_H */ 119