1TF-A Build Instructions for Marvell Platforms 2============================================= 3 4This section describes how to compile the Trusted Firmware-A (TF-A) project for Marvell's platforms. 5 6Build Instructions 7------------------ 8(1) Set the cross compiler 9 10 .. code:: shell 11 12 > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu- 13 14(2) Set path for FIP images: 15 16Set U-Boot image path (relatively to TF-A root or absolute path) 17 18 .. code:: shell 19 20 > export BL33=path/to/u-boot.bin 21 22For example: if U-Boot project (and its images) is located at ``~/project/u-boot``, 23BL33 should be ``~/project/u-boot/u-boot.bin`` 24 25 .. note:: 26 27 *u-boot.bin* should be used and not *u-boot-spl.bin* 28 29Set MSS/SCP image path (mandatory only for A7K/8K/CN913x) 30 31 .. code:: shell 32 33 > export SCP_BL2=path/to/mrvl_scp_bl2*.img 34 35(3) Armada-37x0 build requires WTP tools installation. 36 37See below in the section "Tools and external components installation". 38Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3 39 40 .. code:: shell 41 42 > sudo apt-get install gcc-arm-linux-gnueabi 43 44(4) Clean previous build residuals (if any) 45 46 .. code:: shell 47 48 > make distclean 49 50(5) Build TF-A 51 52There are several build options: 53 54- DEBUG 55 56 Default is without debug information (=0). in order to enable it use ``DEBUG=1``. 57 Must be disabled when building UART recovery images due to current console driver 58 implementation that is not compatible with Xmodem protocol used for boot image download. 59 60- LOG_LEVEL 61 62 Defines the level of logging which will be purged to the default output port. 63 64 LOG_LEVEL_NONE 0 65 LOG_LEVEL_ERROR 10 66 LOG_LEVEL_NOTICE 20 67 LOG_LEVEL_WARNING 30 68 LOG_LEVEL_INFO 40 69 LOG_LEVEL_VERBOSE 50 70 71- USE_COHERENT_MEM 72 73 This flag determines whether to include the coherent memory region in the 74 BL memory map or not. 75 76- LLC_ENABLE 77 78 Flag defining the LLC (L3) cache state. The cache is enabled by default (``LLC_ENABLE=1``). 79 80- LLC_SRAM 81 82 Flag enabling the LLC (L3) cache SRAM support. The LLC SRAM is activated and used 83 by Trusted OS (OP-TEE OS, BL32). The TF-A only prepares CCU address translation windows 84 for SRAM address range at BL31 execution stage with window target set to DRAM-0. 85 When Trusted OS activates LLC SRAM, the CCU window target is changed to SRAM. 86 There is no reason to enable this feature if OP-TEE OS built with CFG_WITH_PAGER=n. 87 Only set LLC_SRAM=1 if OP-TEE OS is built with CFG_WITH_PAGER=y. 88 89- MARVELL_SECURE_BOOT 90 91 Build trusted(=1)/non trusted(=0) image, default is non trusted. 92 93- BLE_PATH 94 95 Points to BLE (Binary ROM extension) sources folder. 96 Only required for A7K/8K/CN913x builds. 97 The parameter is optional, its default value is ``plat/marvell/armada/a8k/common/ble``. 98 99- MV_DDR_PATH 100 101 For A7K/8K/CN913x, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0, 102 it is used for ddr_tool build. 103 104 Usage example: MV_DDR_PATH=path/to/mv_ddr 105 106 The parameter is optional for A7K/8K/CN913x, when this parameter is not set, the mv_ddr 107 sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter 108 is necessary for A37x0. 109 110 For the mv_ddr source location, check the section "Tools and external components installation" 111 112- CP_NUM 113 114 Total amount of CPs (South Bridge) connected to AP. When the parameter is omitted, 115 the build uses the default number of CPs, which is a number of embedded CPs inside the 116 package: 1 or 2 depending on the SoC used. The parameter is valid for OcteonTX2 CN913x SoC 117 family (PLAT=t9130), which can have external CPs connected to the MCI ports. Valid 118 values with CP_NUM are in a range of 1 to 3. 119 120- DDR_TOPOLOGY 121 122 For Armada37x0 only, the DDR topology map index/name, default is 0. 123 124 Supported Options: 125 - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB) 126 - DDR4 1CS (1): DB-88F3720-DDR4-Modular (512MB) 127 - DDR3 2CS (2): EspressoBIN V3-V5 (1GB 2CS) 128 - DDR4 2CS (3): DB-88F3720-DDR4-Modular (4GB) 129 - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB); EspressoBIN V3-V5 (1GB 1CS) 130 - DDR4 1CS (5): EspressoBin V7 (1GB) 131 - DDR4 2CS (6): EspressoBin V7 (2GB) 132 - DDR3 2CS (7): EspressoBin V3-V5 (2GB) 133 - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB 134 135- CLOCKSPRESET 136 137 For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency, 138 default is CPU_800_DDR_800. 139 140 - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz 141 - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz 142 - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz 143 - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz 144 145- BOOTDEV 146 147 For Armada37x0 only, the flash boot device, default is ``SPINOR``. 148 149 Currently, Armada37x0 only supports ``SPINOR``, ``SPINAND``, ``EMMCNORM`` and ``SATA``: 150 151 - SPINOR - SPI NOR flash boot 152 - SPINAND - SPI NAND flash boot 153 - EMMCNORM - eMMC Download Mode 154 155 Download boot loader or program code from eMMC flash into CM3 or CA53 156 Requires full initialization and command sequence 157 158 - SATA - SATA device boot 159 160- PARTNUM 161 162 For Armada37x0 only, the boot partition number, default is 0. 163 164 To boot from eMMC, the value should be aligned with the parameter in 165 U-Boot with name of ``CONFIG_SYS_MMC_ENV_PART``, whose value by default is 166 1. For details about CONFIG_SYS_MMC_ENV_PART, please refer to the U-Boot 167 build instructions. 168 169- WTMI_IMG 170 171 For Armada37x0 only, the path of the WTMI image can point to an image which 172 does nothing, an image which supports EFUSE or a customized CM3 firmware 173 binary. The default image is wtmi.bin that built from sources in WTP 174 folder, which is the next option. If the default image is OK, then this 175 option should be skipped. 176 177- WTP 178 179 For Armada37x0 only, use this parameter to point to wtptools source code 180 directory, which can be found as a3700_utils.zip in the release. Usage 181 example: ``WTP=/path/to/a3700_utils`` 182 183 For example, in order to build the image in debug mode with log level up to 'notice' level run 184 185 .. code:: shell 186 187 > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> all fip 188 189 And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level, 190 the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS, 191 the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command 192 line is as following 193 194 .. code:: shell 195 196 > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \ 197 MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip 198 199 Supported MARVELL_PLATFORM are: 200 - a3700 (for both A3720 DB and EspressoBin) 201 - a70x0 202 - a70x0_amc (for AMC board) 203 - a80x0 204 - a80x0_mcbin (for MacchiatoBin) 205 - t9130 (OcteonTX2 CN913x) 206 207Special Build Flags 208-------------------- 209 210- PLAT_RECOVERY_IMAGE_ENABLE 211 When set this option to enable secondary recovery function when build atf. 212 In order to build UART recovery image this operation should be disabled for 213 A7K/8K/CN913x because of hardware limitation (boot from secondary image 214 can interrupt UART recovery process). This MACRO definition is set in 215 ``plat/marvell/armada/a8k/common/include/platform_def.h`` file. 216 217- DDR32 218 In order to work in 32bit DDR, instead of the default 64bit ECC DDR, 219 this flag should be set to 1. 220 221For more information about build options, please refer to the 222:ref:`Build Options` document. 223 224 225Build output 226------------ 227Marvell's TF-A compilation generates 7 files: 228 229 - ble.bin - BLe image 230 - bl1.bin - BL1 image 231 - bl2.bin - BL2 image 232 - bl31.bin - BL31 image 233 - fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images) 234 - boot-image.bin - TF-A image (contains BL1 and FIP images) 235 - flash-image.bin - Image which contains boot-image.bin and SPL image. 236 Should be placed on the boot flash/device. 237 238 239Tools and external components installation 240------------------------------------------ 241 242Armada37x0 Builds require installation of 3 components 243~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 244 245(1) ARM cross compiler capable of building images for the service CPU (CM3). 246 This component is usually included in the Linux host packages. 247 On Debian/Ubuntu hosts the default GNU ARM tool chain can be installed 248 using the following command 249 250 .. code:: shell 251 252 > sudo apt-get install gcc-arm-linux-gnueabi 253 254 Only if required, the default tool chain prefix ``arm-linux-gnueabi-`` can be 255 overwritten using the environment variable ``CROSS_CM3``. 256 Example for BASH shell 257 258 .. code:: shell 259 260 > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi 261 262(2) DDR initialization library sources (mv_ddr) available at the following repository 263 (use the "mv-ddr-devel" branch): 264 265 https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git 266 267(3) Armada3700 tools available at the following repository 268 (use the "A3700_utils-armada-18.12-fixed" branch): 269 270 https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git 271 272Armada70x0 and Armada80x0 Builds require installation of an additional component 273~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 274 275(1) DDR initialization library sources (mv_ddr) available at the following repository 276 (use the "mv-ddr-devel" branch): 277 278 https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git 279