1# 2# Copyright (c) 2019-2020, Linaro Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7CRASH_REPORTING := 1 8 9include lib/libfdt/libfdt.mk 10 11ifeq (${SPM_MM},1) 12NEED_BL32 := yes 13EL3_EXCEPTION_HANDLING := 1 14GICV2_G0_FOR_EL3 := 1 15endif 16 17# Enable new version of image loading on QEMU platforms 18LOAD_IMAGE_V2 := 1 19 20ifeq ($(NEED_BL32),yes) 21$(eval $(call add_define,QEMU_LOAD_BL32)) 22endif 23 24PLAT_QEMU_PATH := plat/qemu/qemu_sbsa 25PLAT_QEMU_COMMON_PATH := plat/qemu/common 26PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 27 -I${PLAT_QEMU_COMMON_PATH}/include \ 28 -I${PLAT_QEMU_PATH}/include \ 29 -Iinclude/common/tbbr 30 31PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH} 32 33PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \ 34 ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \ 35 drivers/arm/pl011/${ARCH}/pl011_console.S 36 37include lib/xlat_tables_v2/xlat_tables.mk 38PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} 39 40BL1_SOURCES += drivers/io/io_semihosting.c \ 41 drivers/io/io_storage.c \ 42 drivers/io/io_fip.c \ 43 drivers/io/io_memmap.c \ 44 lib/semihosting/semihosting.c \ 45 lib/semihosting/${ARCH}/semihosting_call.S \ 46 ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ 47 ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ 48 ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c 49 50BL1_SOURCES += lib/cpus/aarch64/cortex_a57.S 51 52BL2_SOURCES += drivers/io/io_semihosting.c \ 53 drivers/io/io_storage.c \ 54 drivers/io/io_fip.c \ 55 drivers/io/io_memmap.c \ 56 lib/semihosting/semihosting.c \ 57 lib/semihosting/${ARCH}/semihosting_call.S \ 58 ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ 59 ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ 60 ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \ 61 common/fdt_fixup.c \ 62 $(LIBFDT_SRCS) 63ifeq (${LOAD_IMAGE_V2},1) 64BL2_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \ 65 ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \ 66 common/desc_image_load.c 67endif 68 69# Include GICv3 driver files 70include drivers/arm/gic/v3/gicv3.mk 71 72QEMU_GIC_SOURCES := ${GICV3_SOURCES} \ 73 plat/common/plat_gicv3.c \ 74 ${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c 75 76BL31_SOURCES += lib/cpus/aarch64/cortex_a57.S \ 77 lib/semihosting/semihosting.c \ 78 lib/semihosting/${ARCH}/semihosting_call.S \ 79 plat/common/plat_psci_common.c \ 80 ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \ 81 ${PLAT_QEMU_COMMON_PATH}/topology.c \ 82 ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \ 83 ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \ 84 ${QEMU_GIC_SOURCES} 85ifeq (${SPM_MM},1) 86 BL31_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_spm.c 87endif 88 89SEPARATE_CODE_AND_RODATA := 1 90ENABLE_STACK_PROTECTOR := 0 91ifneq ($(ENABLE_STACK_PROTECTOR), 0) 92 PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c 93endif 94 95MULTI_CONSOLE_API := 1 96 97# Disable the PSCI platform compatibility layer 98ENABLE_PLAT_COMPAT := 0 99 100# Use known base for UEFI if not given from command line 101# By default BL33 is at FLASH1 base 102PRELOADED_BL33_BASE ?= 0x10000000 103 104# Qemu SBSA plafrom only support SEC_SRAM 105BL32_RAM_LOCATION_ID = SEC_SRAM_ID 106$(eval $(call add_define,BL32_RAM_LOCATION_ID)) 107 108# Don't have the Linux kernel as a BL33 image by default 109ARM_LINUX_KERNEL_AS_BL33 := 0 110$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) 111$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) 112 113ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE 114$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) 115 116# Do not enable SVE 117ENABLE_SVE_FOR_NS := 0 118